Clock summary – Altera Stratix V Avalon-ST User Manual
Page 114
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Clock Summary
Table 6-4: Clock Summary
Name
Frequency
Clock Domain
coreclkout_hip
62.5, 125 or 250 MHz
Avalon-ST interface between the Transaction and
Application Layers.
pld_clk
125 or 250 MHz
Application and Transaction Layers.
refclk
100 or 125 MHz
SERDES (transceiver). Dedicated free running input
clock to the SERDES block.
reconfig_xcvr_clk
100 –125 MHz
Transceiver Reconfiguration Controller.
6-8
Clock Summary
UG-01097_sriov
2014.12.15
Altera Corporation
Reset and Clocks
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