Altera Stratix V Avalon-ST User Manual
Page 150
Figure A-3: Memory Read Request, 64-Bit Addressing
Memory Read Request, 64-Bit Addressing
3
+
2
+
1
+
0
+
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
6
5 4 3 2 1 0 7 6 5 4 3 2 1 0
Byte 0
0 0 0 0 0 0 0 0 0
TC
0 0 0 0
TD
EP
Att
r
0 0
Length
Byte 4
E
B
t
s
r
i
F
E
B
t
s
a
L
g
a
T
D
I
r
e
t
s
e
u
q
e
R
Byte 8
Address[63:32]
Byte 12
Address[31:2]
0 0
Figure A-4: Memory Read Request, Locked 64-Bit Addressing
Memory Read Request, Locked 64-Bit Addressing
3
+
2
+
1
+
0
+
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6
5 4 3 2 1 0 7 6 5 4 3 2 1 0
Byte 0
0 0 1 0 0 0 0 1 0
TC
0 0 0 0
T
EP
Att
r
0 0
Length
Byte 4
E
B
t
s
r
i
F
E
B
t
s
a
L
g
a
T
D
I
r
e
t
s
e
u
q
e
R
Byte 8
Address[63:32]
Byte 12
Address[31:2]
0 0
Figure A-5: Configuration Read Request Root Port (Type 1)
Configuration Read Request Root Port (Type 1)
3
+
2
+
1
+
0
+
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
6
5 4 3 2 1 0 7 6 5 4 3 2 1
0
Byte 0
0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0
TD
EP
0 0 0 0 0 0 0 0 0 0 0 0 0
1
Byte 4
g
a
T
D
I
r
e
t
s
e
u
q
e
R
0 0 0 0
First BE
Byte 8
Bus Number
Device No
Func
0
0
0 0
Ext Reg
Register No
0 0
Byte 12
Reserved
A-2
Transaction Layer Packet (TLP) Header Formats
UG-01097_sriov
2014.12.15
Altera Corporation
Transaction Layer Packet (TLP) Header Formats