Design implementation – Altera Stratix V Avalon-ST User Manual
Page 136
Design Implementation
10
2014.12.15
UG-01097_sriov
Completing your design includes additional steps to specify analog properties, pin assignments, and
timing constraints.
Making Analog QSF Assignments Using the Assignment Editor
You specify the analog parameters using the Quartus II Assignment Editor, the Pin Planner, or through
the Quartus II Settings File
.(qsf)
.
Table 10-1: Power Supply Voltage Requirements
Required PCB voltages depend on the PLL type and data rate.
Data Rate
Speed Grade
PLL
Type
V
CCR_GXB
and V
CCT_
GXB
V
CCA_
GXB
Gen1 or Gen2
All
ATX
1.0 V
3.0 V
Gen1 or Gen2—DFE, AEQ and EyeQ not used
C2L, C3, C4, I2L,
I3, I3L, and I4
CMU
0.85 V
2.5 V
Gen1 or Gen2—DFE, AEQ and EyeQ not used
C1, C2, I2
CMU
0.90 V
2.5 V
Gen3
All
ATX
1.0 V
3.0 V
Gen3
All
CMU
1.0 V
3.0 V
The Quartus II software provides default values for analog parameters. You can change the defaults using
the Assignment Editor or the Pin Planner. You can also edit your
.qsf
directly or by typing commands in
the Quartus II Tcl Console.
The following example shows how to change the value of the voltages required:
1. On the Assignments menu, select Assignment Editor. The Assignment Editor appears.
2. Complete the following steps for each pin requiring the V
CCR_GXB
and V
CCT_GXB
voltage:
a. Double-click in the Assignment Name column and scroll to the bottom of the available
assignments.
b. Select VCCR_GXB/VCCT_GXB Voltage.
c. In the Value column, select 1_0V from the list.
3. Complete the following steps for each pin requiring the V
CCA_GXB
voltage:
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