Setting up and verifying msi interrupts, Masking msi interrupts – Altera Stratix V Avalon-ST User Manual
Page 115
Programming and Testing SR-IOV Bridge MSI
Interrupts
7
2014.12.15
UG-01097_sriov
Related Information
Setting Up and Verifying MSI Interrupts
The following procedure specifies and tests MSI interrupts. Perform the first five steps once, during or
after enumeration.
1. Disable legacy interrupts by setting
Interrupt Disable
bit of the
Command
register using a Configura‐
tion Write Request. The
Interrupt Disable
bit is bit 10 of the
Command
register.
2. Enable MSI interrupts by setting the
MSI enable
of the
MSI Control
register using a Configuration
Write Request. The
MSI enable
is bit 16 of 0x050.
3. Set up the MSI Address and MSI Data using a Configuration Write Request.
4. Specify the number of MSI vectors in the
Multiple Message Enable
field of the
MSI Control
register using Configuration Write Request.
5. Unmask the bits associated with MSI vectors in the previous step register using Configuration Write
Request..
6. Send MSI requests via the
app_msi*
interface.
7. Verify that
app_msi_status[1:0]=0
when
app_msi_ack=1
.
8. Expect a Memory Write TLP request with the address and data matching those previously specified.
You can build on this procedure to verify that the Message TLP is dropped and
app_msi_status = 0x2
if
either of the following conditions are true:
• The MSI capability is present, but the
MSI enable
bit is not set.
• The MSI capability is disabled, but the application sends an MSI request.
Masking MSI Interrupts
If Application Layer sends MSI interrupt when the corresponding mask bit is set, the bridge does not send
this MSI interrupt to the host. Instead, the bridge sets the corresponding pending bit internally. The core
sends this interrupt if its corresponding mask bit is cleared and the previous pending bit is set. The
following procedure illustrates how to mask and unmask interrupts. The first four steps are the same as
for
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