Altera Stratix V Avalon-ST User Manual
Page 58
The LMI interface is synchronized to
pld_clk
and runs at frequencies up to 250 MHz. The LMI address is
the same as the Configuration Space address. The read and write data are always 32 bits. The LMI
interface provides the same access to Configuration Space registers as Configuration TLP requests.
Register bits have the same attributes, (read only, read/write, and so on) for accesses from the LMI
interface and from Configuration TLP requests.
When a LMI write has a timing conflict with configuration TLP access, the configuration TLP accesses
have higher priority. LMI writes are held and executed when configuration TLP accesses are no longer
pending. An acknowledge signal is sent back to the Application Layer when the execution is complete.
All LMI reads are also held and executed when no configuration TLP requests are pending. The LMI
interface supports two operations: local read and local write. The timing for these operations complies
with the Avalon-MM protocol described in the Avalon Interface Specifications. LMI reads can be issued at
any time to obtain the contents of any Configuration Space register. LMI write operations are not
recommended for use during normal operation. The Configuration Space registers are written by requests
received from the PCI Express link and there may be unintended consequences of conflicting updates
from the link and the LMI interface. LMI Write operations are provided for AER header logging, and
debugging purposes only.
Table 4-11: LMI Interface
Signal
Direction
Description
lmi_dout[31:0]
Output
Data outputs. Valid when
lmi_ack
has been asserted.
lmi_rden
Input
Read enable input.
lmi_wren
Input
Write enable input.
lmi_ack
Output
Acknowledgment for a read or write operation. The SR-IOV
Bridge asserts this output for one cycle after it has completed the
read or write operation. For read operations, the assertion of
lmi_ack
also indicates the presence of valid data on
lmi_dout
.
lmi_addr[11:0]
Input
Byte address of 32-bit configuration register. Bits [1:0] are not
used.
lmi_func[8:0]
Input
Bit [8] directs the LMI read or write operation to either the Hard
IP or the Function configuration spaces implemented in the SR-
IOV Bridge. The following encodings are defined:
• 1b'0: LMI access to registers in Hard IP block
• 1'b1: Access to configuration registers in the SR-IOV Bridge
Bits [7:0] specify the function number corresponding to the LMI
access. Used only when the LMI access is to a configuration
register in the SR-IOV Bridge.
lmi_din[31:0]
Input
Data inputs.
UG-01097_sriov
2014.12.15
LMI Signals
4-23
Interfaces and Signal Descriptions
Altera Corporation