Transceiver phy ip reconfiguration – Altera Stratix V Avalon-ST User Manual
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Transceiver PHY IP Reconfiguration
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2014.12.15
UG-01097_sriov
As silicon progresses towards smaller process nodes, circuit performance is affected by variations due to
process, voltage, and temperature (PVT). Consequently, Gen3 designs require offset cancellation and
adaptive equalization (AEQ) to ensure correct operation. Altera’s Qsys example designs all include
Transceiver Reconfiguration Controller and Altera PCIe Reconfig Driver IP cores that automatically
perform these functions during the LTSSM equalization states.
Connecting the Transceiver Reconfiguration Controller IP Core
The Transceiver Reconfiguration Controller IP Core is available for V-series devices and can be found in
the Interface Protocols/Transceiver PHY category in the IP Catalog. When you instantiate the
Transceiver Reconfiguration Controller the Enable offset cancellation block and Enable PLL calibration
options are enabled by default. For Gen3 variants, you should also turn on Enable adaptive equalization
(AEQ) block.
Figure 11-1: Altera Transceiver Reconfiguration Controller Connectivity
The following figure shows the connections between the Transceiver Reconfiguration Controller instance
and the PHY IP Core for PCI Express instance for a ×4 variant.
Avalon-MM
Slave Interface
PHY IP Core for PCI Express
Lane 2
Lane 3
Lane 1
Lane 0
TX PLL
Transceiver Bank
to and from
Embedded
Controller
100-125 MHz
Transceiver Reconfiguration Controller
(Unused)
mgmt_clk_clk
mgmt_rst_reset
reconfig_mgmt_address[6:0]
reconfig_mgmt_writedata[31:0]
reconfig_mgmt_readdata[31:0]
reconfig_mgmt_write
reconfig_mgmt_read
reconfig_mgmt_waitrequest
reconfig_to_xcvr
reconfig_from_xcvr
Hard IP for PCI Express Variant
Hard IP for PCI Express
Trans-
action
Data
Link
PHY
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