Document Outline

• Contents
  • Figures
  • Tables
  • Revision History
• Preface
  • P.1 About the EP93xx User’s Guide
  • P.2 Related Documents from Cirrus Logic
  • P.3 Reference Documents
  • P.4 Notational Conventions
  • P.5 Register Example
• Introduction
  • 1.1 Introduction
  • 1.2 EP93xx Features
  • 1.3 EP93xx Processor Applications
  • 1.4 EP93xx Processor Highlights
    • 1.4.1 High-Performance ARM920T Core
    • 1.4.2 MaverickCrunch™ Co-processor for Ultra-Fast Math Processing
    • 1.4.3 MaverickKey™ Unique ID Secures Digital Content in OEM Designs
    • 1.4.4 Integrated Multi-Port USB 2.0 Full Speed Hosts with Transceivers
    • 1.4.5 Integrated Ethernet MAC Reduces BOM Costs
    • 1.4.6 8x8 Keypad Interface Reduces BOM Costs
    • 1.4.7 Multiple Booting Mechanisms Increase Flexibility
    • 1.4.8 Abundant General Purpose I/Os Build Flexible Systems
    • 1.4.9 General-Purpose Memory Interface (SDRAM, SRAM, ROM, FLASH)
    • 1.4.10 12-Bit Analog-to-Digital Converter (ADC) Provides an Integrated Touch-Screen Interface or General ADC Functionality
    • 1.4.11 Raster Analog / LCD Controller
    • 1.4.12 Graphics Accelerator
    • 1.4.13 PCMCIA Interface
• ARM920T Core and Advanced High-Speed Bus (AHB)
  • 2.1 Introduction
  • 2.2 Overview: ARM920T Core
    • 2.2.1 Features
    • 2.2.2 Block Diagram
    • 2.2.3 Operations
      • 2.2.3.1 ARM9TDMI Core
      • 2.2.3.2 Memory Management Unit
      • 2.2.3.3 Cache and Write Buffer
    • 2.2.4 Co-processor Interface
    • 2.2.5 AMBA AHB Bus Interface Overview
    • 2.2.6 AHB Implementation Details
    • 2.2.7 Memory and Bus Access Errors
    • 2.2.8 Bus Arbitration
      • 2.2.8.1 Main AHB Bus Arbiter
      • 2.2.8.2 SDRAM Slave Arbiter
      • 2.2.8.3 EBI Bus Arbiter
  • 2.3 AHB Decoder
    • 2.3.1 AHB Slave
    • 2.3.2 AHB-to-APB Bridge
      • 2.3.2.1 Function and Operation of the AHB-to-APB Bridge
    • 2.3.3 APB Slave
    • 2.3.4 Register Definitions
    • 2.3.5 Memory Map
    • 2.3.6 Internal Register Map
      • 2.3.6.1 Memory Access Rules
• MaverickCrunch Co-Processor
  • 3.1 Introduction
    • 3.1.1 Features
    • 3.1.2 Operational Overview
    • 3.1.3 Pipelines and Latency
    • 3.1.4 Data Registers
    • 3.1.5 Integer Saturation Arithmetic
    • 3.1.6 Comparisons
  • 3.2 Programming Examples
    • 3.2.1 Example 1
      • 3.2.1.1 Setup Code
      • 3.2.1.2 C Code
      • 3.2.1.3 Accessing MaverickCrunch with ARM Co-Processor Instructions
      • 3.2.1.4 MaverickCrunch Assembly Language Instructions
    • 3.2.2 Example 2
      • 3.2.2.1 C Code
      • 3.2.2.2 MaverickCrunch Assembly Language Instructions
  • 3.3 DSPSC Register
  • 3.4 ARM Co-Processor Instruction Format
  • 3.5 Instruction Set for the MaverickCrunch Co-Processor
    • 3.5.1 Load and Store Instructions
    • 3.5.2 Move Instructions
    • 3.5.3 Accumulator and DSPSC Move Instructions
    • 3.5.4 Copy and Conversion Instructions
    • 3.5.5 Shift Instructions
    • 3.5.6 Compare Instructions
    • 3.5.7 Floating Point Arithmetic Instructions
    • 3.5.8 Integer Arithmetic Instructions
    • 3.5.9 Accumulator Arithmetic Instructions
• Boot ROM
  • 4.1 Introduction
    • 4.1.1 Boot ROM Hardware Operational Overview
      • 4.1.1.1 Memory Map
    • 4.1.2 Boot ROM Software Operational Overview
      • 4.1.2.1 Image Header
      • 4.1.2.2 Boot Algorithm
      • 4.1.2.3 Flowchart
  • 4.2 Boot Options
    • 4.2.1 UART Boot
    • 4.2.2 SPI Boot
    • 4.2.3 FLASH Boot
    • 4.2.4 SDRAM or SyncFLASH Boot
    • 4.2.5 Synchronous Memory Operation
• System Controller
  • 5.1 Introduction
    • 5.1.1 System Startup
    • 5.1.2 System Reset
    • 5.1.3 Hardware Configuration Control
    • 5.1.4 Software System Configuration Options
    • 5.1.5 Clock Control
      • 5.1.5.1 Oscillators and Programmable PLLs
      • 5.1.5.2 Bus and Peripheral Clock Generation
      • 5.1.5.3 Steps for Clock Configuration
    • 5.1.6 Power Management
      • 5.1.6.1 Clock Gatings
      • 5.1.6.2 System Power States
    • 5.1.7 Interrupt Generation
  • 5.2 Registers
• Vectored Interrupt Controller
  • 6.1 Introduction
    • 6.1.1 Interrupt Priority
    • 6.1.2 Interrupt Configuration
    • 6.1.3 Interrupt Details
  • 6.2 Registers
• Raster Engine With Analog/LCD Integrated Timing and Interface
  • 7.1 Introduction
  • 7.2 Features
  • 7.3 Raster Engine Features Overview
    • 7.3.1 Hardware Blinking
    • 7.3.2 Color Look-Up Tables
    • 7.3.3 Grayscale/Color Generation for Monochrome/Passive Low Color Displays
    • 7.3.4 Frame Buffer Organization
    • 7.3.5 Frame Buffer Memory Size
    • 7.3.6 Pulse Width Modulated Brightness
    • 7.3.7 Hardware Cursor
  • 7.4 Functional Details
    • 7.4.1 VILOSATI (Video Image Line Output Scanner and Transfer Interface)
    • 7.4.2 Video FIFO
    • 7.4.3 Video Pixel MUX
    • 7.4.4 Blink Function
    • 7.4.5 Color Look-Up-Tables
    • 7.4.6 Color RGB Mux
    • 7.4.7 Pixel Shift Logic
    • 7.4.8 Grayscale/Color Generator for Monochrome/Passive Low Color Displays
      • 7.4.8.1 HORZ_CNT3, HORZ_CNT4 Counters
      • 7.4.8.2 VERT_CNT3, VERT_CNT4 Counters
      • 7.4.8.3 FRAME_CNT3, FRAME_CNT4 Counters
      • 7.4.8.4 HORZ_CNTx (pixel) timing
      • 7.4.8.5 VERT_CNTx (line) timing
      • 7.4.8.6 FRAME_CNTx timing
      • 7.4.8.7 Grayscale Look-Up Table (GrySclLUT)
      • 7.4.8.8 GrySclLUT Timing Diagram
    • 7.4.9 Hardware Cursor
      • 7.4.9.1 Registers Used for Cursor
    • 7.4.10 Video Timing
      • 7.4.10.1 Setting the Video Memory Parameters
      • 7.4.10.2 PixelMode
    • 7.4.11 Blink Logic
      • 7.4.11.1 BlinkRate
      • 7.4.11.2 Defining Blink Pixels
      • 7.4.11.3 Types of Blinking
    • 7.4.12 Color Mode Definition
      • 7.4.12.1 Pixel Look-up Table Mode
      • 7.4.12.2 Triple 8-bit Color Definition Mode
      • 7.4.12.3 16-bit 565 Color Definition Mode
      • 7.4.12.4 16-bit 555 Color Definition Mode
  • 7.5 Registers
• Graphics Accelerator
  • 8.1 Overview
  • 8.2 Block Processing Modes
    • 8.2.1 Copy
      • 8.2.1.1 Transparency
      • 8.2.1.2 Logical Mask
      • 8.2.1.3 Logical Destination
      • 8.2.1.4 Operation Precedence
    • 8.2.2 Remapping
    • 8.2.3 Block Fills
    • 8.2.4 Packed Memory Transfer
  • 8.3 Line Draws
    • 8.3.1 Breshenham Line Draws
    • 8.3.2 Pixel Step Line Draws
  • 8.4 Memory Organization for Graphics Accelerator
    • 8.4.1 Memory Organization for 1 Bit Per Pixel (bpp)
    • 8.4.2 Memory Organization for 4-Bits Per Pixel
    • 8.4.3 Memory Organization for 8-Bits Per Pixel
    • 8.4.4 Memory Organization for 16-Bits Per Pixel
    • 8.4.5 Memory Organization for 24-Bits Per Pixel
    • 8.4.6 Memory Map Access
  • 8.5 Register Programming
    • 8.5.1 Word Count
      • 8.5.1.1 Example: 8 BPP mode
      • 8.5.1.2 Example: 24 BPP (packed) mode
    • 8.5.2 Pixel End and Start
      • 8.5.2.1 4 BPP Word Layout
      • 8.5.2.2 8 BPP Word Layout
      • 8.5.2.3 16 BPP WORD Layout
      • 8.5.2.4 24 BPP mode
  • 8.6 Register Usage
    • 8.6.1 Breshenham’s Algorithm Line Draw
    • 8.6.2 Example of Breshenham’s Algorithm Line Draw
    • 8.6.3 Block Fill Function
    • 8.6.4 Block Copy Function
      • 8.6.4.1 Example of Block Copy
  • 8.7 Registers
• 1/10/100 Mbps Ethernet LAN Controller
  • 9.1 Introduction
    • 9.1.1 Detailed Description
      • 9.1.1.1 Host Interface and Descriptor Processor
      • 9.1.1.2 Reset and Initialization
      • 9.1.1.3 Power-down Modes
      • 9.1.1.4 Address Space
    • 9.1.2 MAC Engine
      • 9.1.2.1 Data Encapsulation
    • 9.1.3 Packet Transmission Process
      • 9.1.3.1 Carrier Deference
    • 9.1.4 Transmit Back-Off
      • 9.1.4.1 Transmission
      • 9.1.4.2 The FCS Field
      • 9.1.4.3 Bit Order
      • 9.1.4.4 Destination Address (DA) Filter
      • 9.1.4.5 Perfect Address Filtering
      • 9.1.4.6 Hash Filter
      • 9.1.4.7 Flow Control
      • 9.1.4.8 Receive Flow Control
      • 9.1.4.9 Transmit Flow Control
      • 9.1.4.10 Rx Missed and Tx Collision Counters
      • 9.1.4.11 Accessing the MII
  • 9.2 Descriptor Processor
    • 9.2.1 Receive Descriptor Processor Queues
    • 9.2.2 Receive Descriptor Queue
    • 9.2.3 Receive Status Queue
      • 9.2.3.1 Receive Status Format
      • 9.2.3.2 Receive Flow
      • 9.2.3.3 Receive Errors
      • 9.2.3.4 Receive Descriptor Data/Status Flow
      • 9.2.3.5 Receive Descriptor Example
      • 9.2.3.6 Receive Frame Pre-Processing
      • 9.2.3.7 Transmit Descriptor Processor Queues
      • 9.2.3.8 Transmit Descriptor Queue
      • 9.2.3.9 Transmit Descriptor Format
      • 9.2.3.10 Transmit Status Queue
      • 9.2.3.11 Transmit Status Format
      • 9.2.3.12 Transmit Flow
      • 9.2.3.13 Transmit Errors
      • 9.2.3.14 Transmit Descriptor Data/Status Flow
    • 9.2.4 Interrupts
      • 9.2.4.1 Interrupt Processing
    • 9.2.5 Initialization
      • 9.2.5.1 Interrupt Processing
      • 9.2.5.2 Receive Queue Processing
      • 9.2.5.3 Transmit Queue Processing
      • 9.2.5.4 Other Processing
      • 9.2.5.5 Transmit Restart Process
  • 9.3 Registers
• DMA Controller
  • 10.1 Introduction
    • 10.1.1 DMA Features List
    • 10.1.2 Managing Data Transfers Using a DMA Channel
    • 10.1.3 DMA Operations
      • 10.1.3.1 Memory-to-Memory Channels
      • 10.1.3.2 Memory-to-Peripheral Channels
    • 10.1.4 Internal M2P or P2M AHB Master Interface Functional Description
    • 10.1.5 M2M AHB Master Interface Functional Description
      • 10.1.5.1 Software Trigger Mode
      • 10.1.5.2 Hardware Trigger Mode for Internal Peripherals (SSP and IDE) and for External Peripherals without Handshaking Signals
      • 10.1.5.3 Hardware Trigger Mode for External Peripherals with Handshaking Signals
    • 10.1.6 AHB Slave Interface Limitations
    • 10.1.7 Interrupt Interface
    • 10.1.8 Internal M2P/P2M Data Unpacker/Packer Functional Description
    • 10.1.9 Internal M2P/P2M DMA Functional Description
      • 10.1.9.1 Internal M2P/P2M DMA Buffer Control Finite State Machine
      • 10.1.9.2 Data Transfer Initiation and Termination
    • 10.1.10 M2M DMA Functional Description
      • 10.1.10.1 M2M DMA Control Finite State Machine
      • 10.1.10.2 M2M Buffer Control Finite State Machine
      • 10.1.10.3 Data Transfer Initiation
      • 10.1.10.4 Data Transfer Termination
      • 10.1.10.5 Memory Block Transfer
      • 10.1.10.6 Bandwidth Control
      • 10.1.10.7 External DMA Request (DREQ) Mode
    • 10.1.11 DMA Data Transfer Size Determination
      • 10.1.11.1 Software Initiated M2M and M2P/P2M Transfers
      • 10.1.11.2 Hardware-Initiated M2M Transfers
    • 10.1.12 Buffer Descriptors
      • 10.1.12.1 Internal M2P/P2M Channel Rx Buffer Descriptors
      • 10.1.12.2 Internal M2P/P2M Channel Tx Buffer Descriptors
      • 10.1.12.3 M2M Channel Buffer Descriptors
    • 10.1.13 Bus Arbitration
  • 10.2 Registers
    • 10.2.1 DMA Controller Memory Map
    • 10.2.2 Internal M2P/P2M Channel Register Map
• Universal Serial Bus Host Controller
  • 11.1 Introduction
    • 11.1.1 Features
  • 11.2 Overview
    • 11.2.1 Data Transfer Types
    • 11.2.2 Host Controller Interface
      • 11.2.2.1 Communication Channels
      • 11.2.2.2 Data Structures
    • 11.2.3 Host Controller Driver Responsibilities
      • 11.2.3.1 Host Controller Management
      • 11.2.3.2 Bandwidth Allocation
      • 11.2.3.3 List Management
      • 11.2.3.4 Root Hub
    • 11.2.4 Host Controller Responsibilities
      • 11.2.4.1 USB States
      • 11.2.4.2 Frame Management
      • 11.2.4.3 List Processing
    • 11.2.5 USB Host Controller Blocks
      • 11.2.5.1 AHB Slave
      • 11.2.5.2 AHB Master
      • 11.2.5.3 HCI Slave Block
      • 11.2.5.4 HCI Master Block
      • 11.2.5.5 USB State Control
      • 11.2.5.6 Data FIFO
      • 11.2.5.7 List Processor
      • 11.2.5.8 Root Hub and Host SIE
  • 11.3 Registers
• Static Memory Controller
  • 12.1 Introduction
  • 12.2 Static Memory Controller Operation
  • 12.3 PCMCIA Interface (EP9315 Processor Only)
  • 12.4 PC Card Memory-Mode Enable Signals
  • 12.5 PC Card Memory Mapping
  • 12.6 Registers
    • 12.6.1 Bank Configuration Registers
    • 12.6.2 PCMCIA Configuration Registers (EP9315 Processor Only)
• SDRAM, SyncROM, and SyncFLASH Controller
  • 13.1 Introduction
  • 13.2 Booting from SyncROM or SyncFLASH
  • 13.3 Address Pin Usage
  • 13.4 SDRAM Initialization
  • 13.5 Programming Mode Register: SDRAM Or SyncROM Device
  • 13.6 SDRAM Self Refresh
    • 13.6.1 Entering Self Refresh Mode
    • 13.6.2 Exiting Self Refresh Mode
  • 13.7 Programming Registers: SyncFLASH Device
  • 13.8 External Synchronous Memory System
    • 13.8.1 Chip Select SDCSN[3:0] Decoding
    • 13.8.2 Address/Data/Control Required by Memory System
  • 13.9 Registers
• UART1 With HDLC and Modem Control Signals
  • 14.1 Introduction
  • 14.2 UART Overview
    • 14.2.1 UART Functional Description
      • 14.2.1.1 AMBA APB Interface
      • 14.2.1.2 DMA Block
      • 14.2.1.3 Register Block
      • 14.2.1.4 Baud Rate Generator
      • 14.2.1.5 Transmit FIFO
      • 14.2.1.6 Receive FIFO
      • 14.2.1.7 Transmit Logic
      • 14.2.1.8 Receive Logic
      • 14.2.1.9 Interrupt Generation Logic
      • 14.2.1.10 Synchronizing Registers and Logic
    • 14.2.2 UART Operation
      • 14.2.2.1 Error Bits
      • 14.2.2.2 Disabling the FIFOs
      • 14.2.2.3 System/diagnostic Loopback Testing
      • 14.2.2.4 UART Character Frame
    • 14.2.3 Interrupts
      • 14.2.3.1 UARTMSINTR
      • 14.2.3.2 UARTRXINTR
      • 14.2.3.3 UARTTXINTR
      • 14.2.3.4 UARTRTINTR
      • 14.2.3.5 UARTINTR
  • 14.3 Modem
  • 14.4 HDLC
    • 14.4.1 Overview of HDLC Modes
    • 14.4.2 Selecting HDLC Modes
    • 14.4.3 HDLC Transmit
    • 14.4.4 HDLC Receive
    • 14.4.5 CRCs
    • 14.4.6 Address Matching
    • 14.4.7 Aborts
    • 14.4.8 DMA
    • 14.4.9 Writing Configuration Registers
  • 14.5 UART1 Package Dependency
    • 14.5.1 Clocking Requirements
    • 14.5.2 Bus Bandwidth Requirements
  • 14.1 Registers
• UART2
  • 15.1 Introduction
  • 15.2 IrDA SIR Block
    • 15.2.1 IrDA SIR Encoder/decoder Functional Description
      • 15.2.1.1 IrDA SIR Transmit Encoder
      • 15.2.1.2 IrDA SIR Receive Decoder
    • 15.2.2 IrDA SIR Operation
      • 15.2.2.1 System/diagnostic Loopback Testing
    • 15.2.3 IrDA Data Modulation
    • 15.2.4 Enabling Infrared (Ir) Modes
  • 15.3 UART2 Package Dependency
    • 15.3.1 Clocking Requirements
    • 15.3.2 Bus Bandwidth Requirements
  • 15.4 Registers
• UART3 With HDLC Encoder
  • 16.1 Introduction
  • 16.2 Implementation Details
    • 16.2.1 UART3 Package Dependency
    • 16.2.2 Clocking Requirements
    • 16.2.3 Bus Bandwidth Requirements
  • 16.3 Registers
• IrDA
  • 17.1 Introduction
  • 17.2 IrDA Interfaces
  • 17.3 Shared IrDA Interface Feature
    • 17.3.1 Overview
    • 17.3.2 Functional Description
      • 17.3.2.1 General Configuration
      • 17.3.2.2 Transmitting Data
      • 17.3.2.3 Receiving Data
      • 17.3.2.4 Special Conditions
    • 17.3.3 Control Information Buffering
  • 17.4 Medium IrDA Specific Features
    • 17.4.1 Introduction
      • 17.4.1.1 Bit Encoding
      • 17.4.1.2 Frame Format
    • 17.4.2 Functional Description
      • 17.4.2.1 Baud Rate Generation
      • 17.4.2.2 Receive Operation
      • 17.4.2.3 Transmit Operation
  • 17.5 Fast IrDA Specific Features
    • 17.5.1 Introduction
      • 17.5.1.1 4PPM Modulation
      • 17.5.1.2 4.0 Mbps FIR Frame Format
    • 17.5.2 Functional Description
      • 17.5.2.1 Baud Rate Generation
      • 17.5.2.2 Receive Operation
      • 17.5.2.3 Transmit Operation
    • 17.5.3 IrDA Connectivity
    • 17.5.4 IrDA Integration Information
      • 17.5.4.1 Enabling Infrared Modes
      • 17.5.4.2 Clocking Requirements
      • 17.5.4.3 Bus Bandwidth Requirements
  • 17.6 Registers
• Timers
  • 18.1 Introduction
    • 18.1.1 Features
    • 18.1.2 16 and 32-bit Timer Operation
      • 18.1.2.1 Free Running Mode
      • 18.1.2.2 Pre-load Mode
    • 18.1.3 40-bit Timer Operation
  • 18.2 Registers
• Watchdog Timer
  • 19.1 Introduction
    • 19.1.1 Watchdog Activation
    • 19.1.2 Clocking Requirements
    • 19.1.3 Reset Requirements
    • 19.1.4 Watchdog Status
  • 19.1 Registers
• Real Time Clock With Software Trim
  • 20.1 Introduction
    • 20.1.1 Software Trim
      • 20.1.1.1 Software Compensation
      • 20.1.1.2 Oscillator Frequency Calibration
      • 20.1.1.3 RTCSWComp Value Determination
      • 20.1.1.4 Example - Measured Value Split Into Integer and Fractional Component
      • 20.1.1.5 Maximum Error Calculation vs. Real Time Clock Accuracy
      • 20.1.1.6 Real-Time Interrupt
    • 20.1.2 Reset Control
  • 20.1 Registers
• I2S Controller
  • 21.1 Introduction
  • 21.2 I2S Transmitter Channel Overview
  • 21.3 I2S Receiver Channel Overview
    • 21.3.1 Receiver FIFO’s
  • 21.4 I2S Master Clock Generation
  • 21.5 I2S Bit Clock Rate Generation
    • 21.5.1 Example of the Bit Clock Generation.
    • 21.5.2 Example of Right Justified LRCK format
  • 21.6 Interrupts
  • 21.7 Registers
    • 21.7.1 I2S TX Registers
    • 21.7.2 I2S RX Registers
    • 21.7.3 I2S Configuration and Status Registers
    • 21.7.4 I2S Global Status Registers
• AC’97 Controller
  • 22.1 Introduction
  • 22.2 Interrupts
    • 22.2.1 Channel Interrupts
      • 22.2.1.1 RIS
      • 22.2.1.2 TIS
      • 22.2.1.3 RTIS
      • 22.2.1.4 TCIS
    • 22.2.2 Global Interrupts
      • 22.2.2.1 CODECREADY
      • 22.2.2.2 WINT
      • 22.2.2.3 GPIOINT
      • 22.2.2.4 GPIOTXCOMPLETE
      • 22.2.2.5 SLOT2INT
      • 22.2.2.6 SLOT1TXCOMPLETE
      • 22.2.2.7 SLOT2TXCOMPLETE
  • 22.3 System Loopback Testing
  • 22.4 Registers
• Synchronous Serial Port
  • 23.1 Introduction
  • 23.2 Features
  • 23.3 SSP Functionality
  • 23.4 SSP Pin Multiplex
  • 23.5 Configuring the SSP
    • 23.5.1 Enabling SSP Operation
    • 23.5.2 Master/Slave Mode
    • 23.5.3 Serial Bit Rate Generation
    • 23.5.4 Frame Format
    • 23.5.5 Texas Instruments® Synchronous Serial Frame Format
    • 23.5.6 Motorola® SPI Frame Format
      • 23.5.6.1 SPO Clock Polarity
      • 23.5.6.2 SPH Clock Phase
    • 23.5.7 Motorola SPI Format with SPO=0, SPH=0
    • 23.5.8 Motorola SPI Format with SPO=0, SPH=1
    • 23.5.9 Motorola SPI Format with SPO=1, SPH=0
    • 23.5.10 Motorola SPI Format with SPO=1, SPH=1
    • 23.5.11 National Semiconductor® Microwire™ Frame Format
      • 23.5.11.1 Setup and Hold Time Requirements on SFRMIN with Respect to SCLKIN in Microwire Mode
  • 23.6 Registers
• Pulse Width Modulator
  • 24.1 Introduction
  • 24.2 Theory of Operation
    • 24.2.1 PWM Programming Examples
      • 24.2.1.1 Example
      • 24.2.1.2 Static Programming (PWM is Not Running) Example
      • 24.2.1.3 Dynamic Programming (PWM is Running) Example
    • 24.2.2 Programming Rules
  • 24.3 Registers
• Analog Touch Screen Interface
  • 25.1 Introduction
  • 25.2 Touch Screen Controller Operation
    • 25.2.1 Touch Screen Scanning: Four-wire and Eight-wire Operation
    • 25.2.2 Five-wire and Seven-wire Operation
    • 25.2.3 Direct Operation
    • 25.2.4 Measuring Analog Input with the Touch Screen Controls Disabled
    • 25.2.5 Measuring Touch Screen Resistance
    • 25.2.6 Polled and Interrupt-Driven Modes
    • 25.2.7 Touch Screen Package Dependency
  • 25.3 Registers
• Keypad Interface
  • 26.1 Introduction
  • 26.2 Theory of Operation
    • 26.2.1 Apparent Key Detection
    • 26.2.2 Scan and Debounce
    • 26.2.3 Interrupt Generation
    • 26.2.4 Low Power Mode
    • 26.2.5 Three-key Reset
  • 26.3 Registers
• IDE Interface
  • 27.1 Introduction
  • 27.2 Theory of Operation
    • 27.2.1 Diagrams and State Machines
    • 27.2.2 PIO Operations
    • 27.2.3 MDMA Operations
    • 27.2.4 UDMA Operations
    • 27.2.5 Performance Considerations
    • 27.2.6 UDMA Example
    • 27.2.7 DMA Request Latency
      • 27.2.7.1 DMA Request Deassertion
      • 27.2.7.2 DMA Request Latency Overview
      • 27.2.7.3 IDE DMA Programming Considerations
    • 27.2.8 IDE Package Dependency
      • 27.2.8.1 System Configuration Constraints
      • 27.2.8.2 Bus Bandwidth Requirements
  • 27.3 Registers
• GPIO Interface
  • 28.1 Introduction
    • 28.1.1 Memory Map
    • 28.1.2 Functional Description
    • 28.1.3 Reset
    • 28.1.4 GPIO Pin Map
  • 28.2 Registers
• Security
  • 29.1 Introduction
  • 29.2 Features
  • 29.3 Contact Information
  • 29.4 Registers
• Glossary
• EP93XX Register List