Cirrus Logic EP93xx - Manual (Page 714)

23-2 DS785UM1
Copyright 2007 Cirrus Logic
Synchronous Serial Port
EP93xx User’s Guide
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23.3 SSP Functionality
The SSP includes a programmable bit rate clock divider and prescaler to generate the serial
output clock SCLKOUT from the input clock SSPCLK. Bit rates are supported to 2MHz and
beyond, subject to choice of frequency for SSPCLK. The maximum bit rate will usually be
determined by peripheral devices.
The SSP operating mode, frame format and size are programmed though the control
registers SSPCR0, SSPCR1.
Three individually maskable interrupt outputs, SSPTXINTR, SSPRXINTR and SSPRORINTR
are generated:
• SSPTXINTR requests servicing of the transmit buffer
• SSPRXINTR requests servicing of the receive buffer
• SSPRORINTR indicates an overrun condition in the receive FIFO.
23.4 SSP Pin Multiplex
The SSP pins are multiplexed and may be used for the I
2
S controller instead of SSP by
setting DeviceCfg.I2SonSSP.
23.5 Configuring the SSP
Following reset, the SSP logic is disabled and must be configured when in this state. Control
registers SSPCR0 and SSPCR1 need to be programmed to configure the peripheral as a
master or slave operating under one of the following protocols:
• Motorola SPI
• Texas Instruments SSI
• National Semiconductor.
The bit rate, derived from the external SSPCLK, requires the programming of the clock
prescale register SSPCPSR. The following procedure must be used to initialize the SSP
function:
1. Set the enable bit (SSE) in register SSPCR1.
2. Write the other SSP configuration registers: SSPCR0 and SSPCPSR.
3. Clear the enable bit (SSE) in register SSPCR1.
4. Set the enable bit (SSE) in register SSPCR1.
23.5.1 Enabling SSP Operation
You can either prime the transmit FIFO, by writing up to eight 16-bit values when the SSP is
disabled, or allow the transmit FIFO service request to interrupt the CPU. Once enabled,
transmission or reception of data begins on the transmit (SSPTXD) and receive (SSPRXD)
pins.