Cirrus Logic EP93xx - Manual (Page 310)

9-8 DS785UM1
Copyright 2007 Cirrus Logic
1/10/100 Mbps Ethernet LAN Controller
EP93xx User’s Guide
9
9
9
The resultant 32 bit field is transmitted on the line with bit X 31 first through X 0 last.
9.1.4.3 Bit Order
In compliance with ISO/IEC 8802-3 section 3.3, each byte is transmitted low order bit first,
except for the CRC, as noted in
Section 9.1.4.2 on page 9--7 .
Figure 9-5. Data Bit Transmission Order
9.1.4.4 Destination Address (DA) Filter
There are two forms of destination address filtering performed by the MAC, perfect filtering,
where the address is checked for an exact match, and hashing, where the address is
checked for inclusion in a group. In addition there is a mode to accept all destination
addresses which is enabled via the RXCtl.PA bit.
9.1.4.5 Perfect Address Filtering
The MAC includes four programmable perfect address filters, as well as the all ones filter for
broadcast frames. The RXCtl register is used to control whether a particular filter is used. The
filters themselves share the same address space and the value in the Address Filter Pointer
register determines which filter is being accessed at any time. The filters are arranged such
that the first is the normal MAC address for the interface, which is also used in the detection
of remote wake-up frames, and may be optionally used to detect pause (flow control) frames.
The primary purpose of the second filter is for the recognition of pause frames. This would
normally be programmed to correspond to the multicast address used for MAC control
frames. The third and fourth filters, provide extra optional address match capabilities, which
can provide the capability of adding extra individual addresses or of providing two multicast
address filters.
D0 D7 D8 D15 D16 D31
Byte
Half-Word
Word
Direction of transmission