10 video timing, 10 video timing -28 – Cirrus Logic EP93xx User Manual
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DS785UM1
Copyright 2007 Cirrus Logic
Raster Engine With Analog/LCD Integrated Timing and Interface
EP93xx User’s Guide
7
7
7
7.4.10 Video Timing
The video timing circuitry consists of a horizontal down counter and a vertical down counter.
Signal timing for a specific video format is generated by programmable values that are
compared to the count values.
An AC signal is generated to support either bias voltage switching for LCDs or a field
indicator for interlaced video. The An AC signal, if ACEN = ‘1’ in the
register, is
output on the P[17] pin. The toggle rate of the AC signal is selected by writing to the
register.
LCD shifting signals, XECL and YSCL, are generated to support simple LCDs. These signals,
if LCDEN = ‘1’ in the
register, are output on pixel data pins P[16] and P[15],
respectively. XECL is generated every 64 pixel clocks. YSCL is the inversion of HSYNCn.
The Raster Engine provides an end of frame interrupt, when enabled, to the interrupt
controller. This interrupt defines when the last information has been sent to the display for the
current frame. It indicates the start of an interval when changes can be made to the LUT or
source for the displayed image without affecting the display. It must be configured as an edge
triggered interrupt. Changes such as a new cursor location or a new screen image location
automatically change at this time, under hardware control. The interval for making LUT
changes, etc. without affecting the displayed image depends on the display’s technology. The
time duration is equal to the vertical blanking interval (VLinesTotal duration - VACTIVE
duration).
In addition, the programmable VCLR and HCLR fields in the
register
are used as
a secondary interrupt during normal operation, where the interrupt can be programmed to
trigger at any vertical and horizontal counter combination.
The frequency of the clock used for video timing and the entire video pipeline must meet the
requirements of the display type. The video clock frequency is selected by writing to the
VidClkDiv
register (see
). The video circuitry is targeted to run up to 132MHz. This
corresponds to a 1280 pixels by 1024 pixels display size, and non-interlaced video at a 80Hz
frame refresh.
Note: Total Bus/SDRAM bandwidth is shared between the Raster Engine and other device
controllers. The pixel depth, display size, and display refresh rate can be limited by the
Bus/SDRAM bandwidth that is available to the Raster Engine.
The programmed values for the video timing section of the raster engine are shown in
Figure 7-9, "Progressive/Dual Scan Video Signals"
Figure 7-10, "Interlaced Video
. Independent horizontal and vertical down counters are used as a reference for all
other signals. The synchronization, blanking, and active video control signalling is generated
by comparing programmed values to the counters.