Cirrus Logic EP93xx - Manual (Page 504)

13-8 DS785UM1
Copyright 2007 Cirrus Logic
SDRAM, SyncROM, and SyncFLASH Controller
EP93xx User’s Guide
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When using a 16-bit wide external memory bus, the following Read addresses must be used
to set up the specified parameters, where H can be 0, C, D, E or F as shown in
Table 13-2 :
• SDRAM default READ Address: 0xH000_6600 — sets WBM=0, TM=0, CAS=3,
Sequential, BL=8
• SFLASH default READ Address: 0xH004_6600 — sets WBM=1, TM=0, CAS=3,
Sequential, BL=8
• SROM default READ Address: 0xH000_C400 — sets RAS=2, CAS=5, Sequential, BL=8
13.6 SDRAM Self Refresh
13.6.1 Entering Self Refresh Mode
When entering the Standby mode, the following actions are carried out by the Synchronous
Memory controller before the processor is stopped:
1. Issue Precharge accesses to all active banks
2. Issue NOP commands
3. SDCLKEN output driven low
4. Issue AUTO REFRESH command
5. Enter SELF REFRESH Mode
13.6.2 Exiting Self Refresh Mode
When coming out of the Standby mode, the following actions are carried out by the
synchronous memory controller before the processor is started:
1. Allow clock stabilization
2. SDCLKEN output driven high
3. Issue ten NOP accesses
4. Issue AUTO REFRESH accesses
5. Exit SELF REFRESH Mode
13.7 Programming Registers: SyncFLASH Device
The programmable registers that are inside a SyncFLASH memory device, can be
programmed in a manner that is similar to programming the Mode register that is inside of an
SDRAM or SyncROM memory device.
The process of programming the SyncFLASH registers begins by writing WBM = ‘1’ to the
appropriate SDRAMDevCfg register to specify that burst-of-four reads and burst-of-one
writes will be used to access the device. Then, write LCR = ‘1’ to the GlConfig register. Doing
so causes the value of a subsequent read address to be used as the data value that is written