Cirrus Logic EP93xx - Manual (Page 265)

DS785UM1 8-1
Copyright 2007 Cirrus Logic
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Chapter 8
8 Graphics Accelerator
8.1 Overview
Note: The chapter applies only to the EP9307 and EP9315 procesors.
The hardware Graphics Accelerator improves graphic performance by handling block copy,
block fill, and hardware line draw functions. The Graphics Accelerator is used to off-load
graphics functions from the ARM Core. Pixel depths supported by the Graphics Accelerator
are 4, 8, 16 or 24 bits per pixel. The 24 bits per pixel mode can be operated as packed (4
pixels every 3 words) or unpacked (1 pixel per word with the high byte unused.) The Block
Copy function of the Graphics Accelerator is similar to a DMA (Direct Memory Access)
transfer that understands:
1. Pixel organization
2. Block width
3. Transparency, and
4. Transformation from 1 bpp (bit per pixel) to higher 4, 8, 16 or 24 bpp.
The Line Draw functions allow for solid lines or dashed lines. The colors for line drawing can
be either foreground color and background color or foreground color with the background
being transparent. The Graphics Accelerator also has an interrupt to indicate completion, or
termination due to error, of the current function.
8.2 Block Processing Modes
The block transfer modes allow transferring blocks of data from the source to the destination.
Block transfers occur between two memory areas that are the same size or from a packed
source to unpacked destination. It is not possible to copy from a large source to a smaller
destination. Three data path options are provided during block transfers:
1. Transparency
2. Logical AND/OR/XOR Mask, and
3. Logical AND/OR/XOR Destination
Since the block transfer features are all in the data path, transfers may be performed with any
combination of the previous functions enabled. When combining functions, the precedence is
Mask logic first, destination logical combination second, and finally transparency.