Cirrus Logic EP93xx - Manual (Page 413)

DS785UM1 10-19
Copyright 2007 Cirrus Logic
DMA Controller
EP93xx User’s Guide
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10.1.12.1 Internal M2P/P2M Channel Rx Buffer Descriptors
Only one Rx buffer descriptor is allocated per transaction. There are five Rx buffer
descriptors, one for each of the five receive channels. Each buffer descriptor allows a
channel double buffering scheme by containing programming for two buffers, that is, two
system buffer base addresses and two buffer byte counts. This ensures that there is always
one free buffer available for transfers to avoid potential data over/under-flow due to software-
introduced latency.
10.1.12.2 Internal M2P/P2M Channel Tx Buffer Descriptors
Only one Tx buffer descriptor is allocated per transaction. There are five Tx buffer
descriptors, one for each of the five transmit channels Each buffer descriptor allows a
channel double buffering scheme by containing programming for two buffers, that is, two
system buffer base addresses and two buffer byte counts. This ensures that there is always
one free buffer available for transfers to avoid potential data over/under-flow due to software
introduced latency.
10.1.12.3 M2M Channel Buffer Descriptors
Only one M2M channel buffer descriptor is allocated per transaction. There are two M2M
buffer descriptors, one for each of the 2 M2M channels. Each buffer descriptor allows a
channel double buffering scheme by containing programming for two buffers, that is, two
source base addresses, two destination base addresses and two buffer byte counts. The
buffers are limited to 64 kBytes (0xFFF). This ensures that there is always one free buffer
available for transfers which avoids potential data overflow/underflow due to software
introduced latency.
10.1.13 Bus Arbitration
When ready to do a transfer, the DMA Controller arbitrates internally between DMA
Channels, then requests AHB bus access to the external AHB bus arbiter. Then a default
setting of M2P having a higher priority than M2M is implemented. The default setting is
programmable and can be changed if required (DMA Arbitration register bit[0] = CHARB).
The channel arbitration scheme is based on rotating priority, the order is as shown below in
Table 10-2 :
Table 10-2. M2P DMA Bus Arbitration
Internal Arbitration Priority
CHARB = 0 CHARB = 1
Highest M2P Ch 0 M2M Ch 0
M2P Ch 1 M2M Ch 1
M2P Ch 2 M2P Ch 0
M2P Ch 3 M2P Ch 1
M2P Ch 4 M2P Ch 2
M2P Ch 5 M2P Ch 3
M2P Ch 6 M2P Ch 4