Cirrus Logic EP93xx User Manual
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DS785UM1
Copyright 2007 Cirrus Logic
Synchronous Serial Port
EP93xx User’s Guide
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SSPCPSR
Address:
0x808A_0010 - Read/Write
Default:
0x0000_0000
Definition:
SSPCPSR is the clock prescale register and specifies the division factor by
which the input SSPCLK should be internally divided before further use.
The value programmed into this register should be an even number between 2
and 254. The least significant bit of the programmed number is hard-coded to
zero. If an odd number is written to this register, data read back from this
register will have the least significant bit as zero.
Bit Descriptions:
RSVD:
Reserved. Unknown During Read.
CPSDVSR:
Clock pre-scale divisor. Should be an even number from 2
to 254, depending on the frequency of SSPCLK. The least
significant bit CPSDVSR[0] always returns zero on reads
since it is hard-coded to 0
SSPIIR / SSPICR
Address:
0x808A_0014 - Read Only
Note: A write to this register clears the receive overrun interrupt, regardless of the data value
written.
Default:
0x0000_0000
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RSVD
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RSVD
CPSDVSR
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RSVD
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RSVD
RORIS
TIS
RIS