Cirrus Logic EP93xx - Manual (Page 106)

3-36 DS785UM1
Copyright 2007 Cirrus Logic
MaverickCrunch Co-Processor
EP93xx User’s Guide
3
3
3
Shift 32-bit Integer Immediate
Definition:
Shift a 32-bit integer by the count specified in the seven bit, two’s complement
immediate value. A positive number indicates a left shift and a negative
number indicates a right shift. This instruction may also be used to copy a 32-
bit integer from one register to another using a shift value of 0.
Mnemonic:
CFSH32<cond> CRd, CRn, Shift[6:0]
Bit Definitions:
CRd: Destination register
CRn: Source register
Shift[6:0]: Shift count.
Shift 64-bit Integer Immediate
Definition:
Shifts a 64-bit integer by a count specifies in the seven bit, two’s complement
immediate value. A positive number indicates a left shift and a negative
number indicates a right shift. This instruction may also be used to copy a 64-
bit integer from one register to another by using a shift value of 0.
Mnemonic:
CFSH64<cond> CRd, CRn, Shift[6:0]
Bit Definitions:
CRd: Destination register
CRn: Source register
Shift[6:0]: Shift count.
3.5.6 Compare Instructions
Compare Single Precision Floating Point
Definition:
Compares two single precision floating point numbers and stores an integer
representing the result in the ARM920T register; the highest four bits of the
integer result match the N, Z, C, and V bits, respectively, in the ARM920T’s
program status register, while the bottom 28 bits are zeros. If Rd = 15, then the
four status bits are stored in the ARM status register, CPSR.
31:28 27:24 23:22 21:20 19:16 15:12 11:8 7:5 4 3:0
cond 1 1 1 0 0 0 0 0 CRn CRd 0 1 0 1 Shift[6:4] 0 Shift[3:0]
31:28 27:24 23:22 21:20 19:16 15:12 11:8 7:5 4 3:0
cond 1 1 1 0 0 0 1 0 CRn CRd 0 1 0 1 Shift[6:4] 0 Shift[3:0]
31:28 27:24 23:22 21 20 19:16 15:12 11:8 7:5 4 3:0
cond 1 1 1 0 0 0 0 1 CRn Rd 0 1 0 0 1 0 0 1 CRm