Cirrus Logic EP93xx - Manual (Page 105)

DS785UM1 3-35
Copyright 2007 Cirrus Logic
MaverickCrunch Co-Processor
EP93xx User’s Guide
3
3
3
Bit Definitions:
CRd: Destination register
CRn: Source register
3.5.5 Shift Instructions
Shift 32-bit Integer
Description:
Shifts a 32-bit integer left or right. The shift count is a two’s complement
integer stored in an ARM register; the count is positive for left shifts and
negative for right shifts. This instruction may also be used to copy a 32-bit
integer from one register to another by using a shift value of 0.
Mnemonic:
CFRSHL32<cond> CRm, CRn, Rd
Bit Definitions:
CRm: Destination register
CRn: Source register
Rd: Shift count register in ARM
Shift 64-bit Integer
Definition:
Shifts a 64-bit integer left or right. The shift count is a two’s complement
integer stored in an ARM register; the count is positive for left shifts and
negative for right shifts. This instruction may also be used to copy a 64-bit
integer from one register to another using a shift value of 0.
Mnemonic:
CFRSHL64<cond> CRm, CRn, Rd
Bit Definitions:
CRm: Destination register
CRn: Source register
Rd: Shift count register in ARM
31:28 27:24 23:22 21 20 19:16 15:12 11:8 7:5 4 3:0
cond 1 1 1 0 0 0 0 0 CRn Rd 0 1 0 1 0 1 0 1 CRm
31:28 27:24 23:22 21 20 19:16 15:12 11:8 7:5 4 3:0
cond 1 1 1 0 0 0 0 0 CRn Rd 0 1 0 1 0 1 1 1 CRm