Cirrus Logic EP93xx - Manual (Page 722)

23-10 DS785UM1
Copyright 2007 Cirrus Logic
Synchronous Serial Port
EP93xx User’s Guide
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• when the SSP is configured as a master, the SSPCTLOE line is driven LOW, enabling
the SCLKOUT pad (active LOW enable)
• when the SSP is configured as a slave, the SSPCTLOE line is driven HIGH, disabling
the SCLKOUT pad (active LOW enable).
If the SSP is enabled and there is valid data within the transmit FIFO, the start of
transmission is signified by the SFRMOUT master signal being driven LOW. The master
SSPTXD output pad is enabled. After a further one half SCLKOUT period, both master and
slave data are enabled onto their respective transmission lines. At the same time, the
SCLKOUT is enabled with a falling edge transition. Data is then captured on the rising edges
and propagated on the falling edges of the SCLKOUT signal.
After all bits have been transferred, in the case of a single word transmission, the SFRMOUT
line is returned to its idle HIGH state one SCLKOUT period after the last bit has been
captured.
For continuous back-to-back transmissions, the SFRMOUT pins remains in its active LOW
state, until the final bit of the last word has been captured, and then returns to its idle state as
described above.
For continuous back-to-back transfers, the SFRMOUT pin is held LOW between successive
data words and termination is the same as that of the single word transfer.
23.5.11 National Semiconductor ® Microwire ™ Frame Format
Figure 23-9 shows the National Semiconductor Microwire frame format, again for a single
frame. Figure 23-10 on page 23-12 shows the same format when back to back frames are
transmitted.
Figure 23-9. Microwire Frame Format (Single Transfer)
SC L K
SFR M
SSPT XD
SSPR XD 0 M S B LSB
4 to 16 bits o utp ut data
t
clkrf
t clk_h igh
t
clk_lo w
t
clk_per
M SB L SB
8-bit co ntro l