Cirrus Logic EP93xx - Manual (Page 635)

DS785UM1 18-1
Copyright 2007 Cirrus Logic
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Chapter 18
18 Timers
18.1 Introduction
The timers are used to control timed events in the system. For example, a wait can be
inserted by setting the timer value to an appropriate value and waiting for the timer interrupt.
The Timers block contains two 16-bit timers, one 32-bit timer and one 40-bit time stamp
debug timer.
18.1.1 Features
The processor has these timer features:
• Two 16-bit timers
• Free running
• Load based
• One 32-bit timer
• Free running
• Load based
• One 40-bit timer
• Free running
18.1.2 16 and 32-bit Timer Operation
The two 16-bit timers are referred to as TC1 and TC2. Each of these timers has an
associated 16-bit read/write data register and a control register. Each counter is loaded with
the value written to the data register immediately. This value will then be decremented on the
next active clock edge to arrive after the write. When the timer counter decrements to “0”, it
will assert the appropriate interrupt. The timer counters can be read at any time. The clock
source and mode is selectable by writing to various bits in the system control register. Clock
sources are 508 kHz and 2 kHz. Both of these clock sources are synchronized to the main
system AHB bus clock (HCLK).
Timer 3 (TC3) has the exact same operation as TC1 and TC2, but it is a 32-bit counter. It has
the same register arrangement as TC1 and TC2, providing a load, value, control and clear
register. The 16- and 32-bit timer counters can operate in two modes, free running mode or
pre-load mode.