Cirrus Logic EP93xx - Manual (Page 755)

DS785UM1 25-17
Copyright 2007 Cirrus Logic
Analog Touch Screen Interface
EP93xx User’s Guide
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5
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25
25.3 Registers
Note: The touch screen controller block decodes APB address bits PADR[6:2] only. If the decode
for the PSEL_HATSH APB block select is a larger block size in the APB decoder, the
registers will be repeated through memory. Touch screen controller registers are intended
to be word accessed only. Since the least significant bytes of the address bus are not
decoded, byte and half word accesses are not allowed and may have unpredictable
results.
Register Descriptions
TSSetup
Address:
0x8090_0000
Default:
0x0000_0000
Table 25-4. Analog Touch Screen Register Memory Map
Address Name
SW
locked
Type Size Description
0x8090_0000 TSSetup No Read/Write 26 bits Analog Resistive Touch Screen controller setup control register.
0x8090_0004 TSXYMaxMin No Read/Write 32 bits Analog Resistive Touch Screen controller max/min register.
0x8090_0008 TSXYResult No Read Only 32 bits Analog Resistive Touch Screen controller result register.
0x8090_000C TSDischarge Write Read/Write 28 bits Analog Resistive Touch Screen controller Switch Matrix control register.
0x8090_0010 TSXSample Write Read/Write 28 bits Analog Resistive Touch Screen controller Switch Matrix control register.
0x8090_0014 TSYSample Write Read/Write 28 bits Analog Resistive Touch Screen controller Switch Matrix control register.
0x8090_0018 TSDirect Write Read/Write 28 bits Analog Resistive Touch Screen controller Switch Matrix control register.
0x8090_001C TSDetect Write Read/Write 28 bits Analog Resistive Touch Screen controller Switch Matrix control register.
0x8090_0020 TSSWLock NA Read/Write
1-bit read
8-bit write
Analog Resistive Touch Screen controller software lock register.
0x8090_0024 TSSetup2 No Read/Write 9 bits Analog Resistive Touch Screen controller setup control register #2.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TDTCT RSVD DLY
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EN DEV NSMP SDLY