Cirrus Logic EP93xx - Manual (Page 400)

10-6 DS785UM1
Copyright 2007 Cirrus Logic
DMA Controller
EP93xx User’s Guide
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10.1.5.2 Hardware Trigger Mode for Internal Peripherals (SSP and IDE) and
for External Peripherals without Handshaking Signals
When a M2M channel is set up to transfer to/from SSP, IDE or an external peripheral, the
transfer width used (that is, the AMBA HSIZE signal) is determined by the peripheral width -
programmed via the CONTROL.PW bits of the channel. This means that the transfers occur
one at a time, as opposed to burst transfer operation for software triggered M2M. Thus the
16-byte data bay which is available for software triggered transfers is never fully utilized - at
most 1 word of it is used (depending on PW bits).
10.1.5.3 Hardware Trigger Mode for External Peripherals with Handshaking
Signals
When a M2M channel is set up to transfer to/from an external peripheral, the transfer width
used (that is, the AMBA HSIZE signal) is determined by the peripheral width - programmed
via the CONTROL.PW bits of the channel. This means that the transfers occur one at a time,
as opposed to burst transfer operation for software triggered M2M. Thus the 16-byte data bay
which is available for software triggered transfers is never fully utilized - at most 1 word of it is
used (depending on PW bits).
10.1.6 AHB Slave Interface Limitations
The AHB slave interface is used to access all control and status registers.
The behavior of the AMBA AHB signals complies with the standard described in AMBA
Specification (Rev 2.0) from ARM Limited. The DMA does not utilize the AHB slave split
capabilities, so does not receive HMASTER or HMASTERLOCK and does not drive HSPLIT.
It does not receive HPROT or HRESP and does not drive HLOCK.
10.1.7 Interrupt Interface
Each of the 12 DMA channels (10 M2P/P2M and 2 M2M) generates a single interrupt signal
which is a combination of the interrupt sources for that channel. There are 3 interrupt
sources, which are enabled in the channel control register (for both M2P/P2M and M2M):
DONE, STALL and NFB.The interrupt signals are ORed before being transmitted to the
DMA_INT output bus. Status of the interrupt bus is reflected in the DMA Global Interrupt
Register (DMAGlInt). The status of each interrupt source per channel is found in the
channel’s interrupt register.
10.1.8 Internal M2P/P2M Data Unpacker/Packer Functional Description
The DMA controller transfers data to and from the system memory in four word bursts. The
peripheral DMA bus protocol is used to transfer data to and from the peripherals as single
bytes. In order to build the quad word bursts from the single bytes received from the
peripheral, the DMA controller uses the Rx Burst Packers. To decompose the quad word
bursts into byte transfers to the peripherals the Tx Burst Un-Packers are used.