4 i2s global status registers, S global status registers, S global status registers i2sglsts – Cirrus Logic EP93xx User Manual
Page 685
DS785UM1
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Copyright 2007 Cirrus Logic
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S Controller
EP93xx User’s Guide
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21
21.7.4 I
2
S Global Status Registers
I
2
S Global Status Registers
I2SGlSts
Address:
0x8082_0008 - Read/Write
Default:
0x0001_2492
Definition:
UART Data Register
Bit Descriptions:
RSVD:
Reserved. Unknown During Read.
Tx0_underflow:
when = 1, TX0 FIFO has underflowed.
Tx1_underflow:
when = 1, TX0 FIFO has underflowed.
Tx2_underflow:
when = 1, TX0 FIFO has underflowed.
Rx0_overflow:
when = 1, RX0 FIFO has overflowed and the FIFO pointer
is currently pointing at the last data received before the
overflow occurred.
Rx1_overflow:
when = 1, RX1 FIFO has overflowed and the FIFO pointer
is currently pointing at the last data received before the
overflow occurred.
Rx2_overflow:
when = 1, RX2 FIFO has overflowed and the FIFO pointer
is currently pointing at the last data received before the
overflow occurred.
Tx0_overflow:
when = 1, the tx0 FIFO is full and an attempt has been
made to write data to it by the APB or DMA. This bit is
cleared by writing a 0 to it.
31
30
29
28
27
26
25
24
23
22
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RSVD
rx2_fif
o_half_
full
rx2_fifo
_empty
rx2_fifo_f
ull
tx2_fifo_h
alf_
empty
tx2_fifo_e
mpty
tx2_fifo_
full
rx1_fifo
_half_
full
rx1_fifo
_empty
rx1_fifo
_full
tx1_fifo_
half_
empty
tx1_fifo_
empty
tx1_fifo_f
ull
rx0_fifo_h
alf_
full
rx0_fifo_e
mpty
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rx0_fifo
_full
tx0_fifo
_half_
empty
tx0_fifo
_empty
tx0_fifo
_full
Rx2_
underflow
Rx1_
underflow
Rx0_
underflow
Tx2_
overflow
Tx1_
overflow
Tx0_
overflow
Rx2_
overflow
Rx1_
overflow
Rx0_
overflow
Tx2_
underflow
Tx1_
underflow
Tx0_
underflow