3 i2s configuration and status registers, Table 21-9. i, S configuration and status registers – Cirrus Logic EP93xx User Manual
Page 681
DS785UM1
21-25
Copyright 2007 Cirrus Logic
I
2
S Controller
EP93xx User’s Guide
2
1
2
1
21
Bit Descriptions:
RSVD:
Reserved. Unknown During Read. Must be written as “0”.
i2s_rx1_EN:
RX1 Channel Enable
I2SRX2En
Address:
0x8082_006C - Read/Write
Default:
0x0000_0000
D
efinition:
RX2 Channel Enable
Bit Descriptions:
RSVD:
Reserved. Unknown During Read. Must be written as “0”.
i2s_rx2_EN:
RX2 Channel Enable
21.7.3 I
2
S Configuration and Status Registers
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RSVD
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RSVD
i2s_rx2_EN
Table 21-9. I
2
S Configuration and Status Registers
Address
Type
Width
Reset Value
Name
Description
0x8082_0000
R/W
7
0x0
I2STXClkCfg
Transmitter clock configuration
register.
0x8082_0004
R/W
7
0x0
I2SRXClkCfg
Receiver clock configuration
register
0x8082_0008
R/W
20
0x12492
I2SGlSts
I
2
S Global Status register. This
reflects the status of the 3 RX
FIFOs and the 3 TX FIFOs.
0x8082_000C
R/W
2
0x0
I2SGlCtrl
I
2
S Global Control register.