2 video fifo, 2 video fifo -9, Figure 7-2. video buffer diagram -9 – Cirrus Logic EP93xx User Manual
Page 191
DS785UM1
7-9
Copyright 2007 Cirrus Logic
Raster Engine With Analog/LCD Integrated Timing and Interface
EP93xx User’s Guide
7
7
7
. For a dual scan display, information from the upper left
corner of the lower half of the display begins at the word address stored in the
register. The
and
registers are used to pre-
load address counters at the beginning of the video frame.
The VILOSATI continues to service the video FIFO until it has transferred an entire screen
image from memory. The size of the screen image is controlled by the values stored in the
register defines the total number of
displayed (active) lines for the video frame. The
register defines the number of
words for each displayed (active) video line. A separate register,
,
defines the word offset in memory between the beginning of each line and the next line.
Setting the VLineStep value larger than the LineLength value provides the capability for
image panning as shown in
.
Figure 7-2. Video Buffer Diagram
7.4.2 Video FIFO
The video FIFO is used to buffer data transferred from the image memory to the Video output
circuitry without stalling the video data stream. The FIFO consists of a dual port RAM with
input and output index counters and control circuitry to operate it as a FIFO memory. The
input data bus width to the FIFO is 32 bits. During half page mode, when the display requires
scan out of the bottom and top half of the screen at the same time (dual scan), top half (or
bottom half) data is stored in every other FIFO location.
When the screen is single scan (scanned out as a single progressive image), FIFO data is
stored sequentially. The FIFO output data bus is 64 bits wide and can output even and odd
Frame Buffer
Displayed Portion
VIDSCRNPAGE
start address
LINELENGTH + 1
VLINESTEP
SC
R
N
L
IN
E
S
+
1
VIDSCRHPG
start address
(Dual Scan mode only)