Cirrus Logic EP93xx - Manual (Page 651)

DS785UM1 20-3
Copyright 2007 Cirrus Logic
Real Time Clock With Software Trim
EP93xx User’s Guide
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20.1.1.4 Example - Measured Value Split Into Integer and Fractional
Component
The manufacturing tester measures the oscillator output to be 33,455.870 Hz. For the integer
portion, 33,455 - 32,768 is 687 cycles over the nominal frequency of the crystal. The integer
pre-load value for the counter should always be chosen so that the actual clock frequency is
faster than the value needed to generate a 1 Hz reference. Therefore, the
RTCSWComp.INT[15:0] value is loaded with the binary equivalent of 33,455-1 or 0x82AE.
The fractional component of the oscillator output was measured to be 0.870 Hz. Software
must adjust the clock so that the average number of cycles that are counted before
generating one 1 Hz clock is 33 455-1.
Because the clock frequency is 0.870 Hz faster than the integer value, the 1 Hz clock
generated by just the integer compensation is slightly faster than needed and may be slowed
down by deleting clocks.
The fractional compensation value must be programmed to delete 0.870 Hz on average to
bring the 1 Hz output frequency down to the proper value. Since the compensation procedure
is performed only every 32 seconds, the value must be set to delete (0.870*32) = 27.84
which, when rounded, is 28 clocks every 32 seconds. The rounded 0.16 cycles per
32 seconds (or 0.005 Hz) represents the error in compensation. The RTCSWComp.DEL[4:0]
fractional compensation value should be loaded with the hexadecimal equivalent of
28 - 1 or 0x1B.
20.1.1.5 Maximum Error Calculation vs. Real Time Clock Accuracy
The maximum error is 0.5½ clocks per 32 seconds. Therefore at 32.768 kHz, the maximum
error is:
(0.5½ clock / 32 sec) x (1 sec / 32,768 clocks nominal) x
(2592000 sec/1month) = 1.24 seconds/month maximum error
To maintain an accuracy of +/- 5 seconds per month the required interval is calculated to be:
(5 seconds/1 month) x (1 month/2,592,000 seconds) = 1.93E-6
= (1 second/32,768 clocks) x (½clock / X-interval seconds)
X-interval = 7.9 seconds
Therefore to maintain a 5-second-per-month accuracy the compensation circuit only has to
adjust within ½ of a 32.768 KHZ clock every 7.9 seconds. This could be done with a 3 bit
clock delete value and an 8 second (3 bits clocked by 1 Hz) counter. However, the
1.24 second per month number is better and has been implemented in this device.
20.1.1.6 Real-Time Interrupt
To allow a Real Time Interrupt to be generated, VIC2 INT[10] has been connected to the 1 Hz
clock. This interrupt should be configured as edge-triggered.