Cirrus Logic EP93xx - Manual (Page 406)

10-12 DS785UM1
Copyright 2007 Cirrus Logic
DMA Controller
EP93xx User’s Guide
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10.1.10.1.5 DMA_BWC_WAIT
The DMA M2M Control FSM enters the DMA_BWC_WAIT state when the byte count is within
15 bytes of a multiple of the BWC value.
The DMA M2M Control FSM stays in this state for one cycle only.
10.1.10.2 M2M Buffer Control Finite State Machine
Figure 10-3. M2M DMA Buffer Finite State Machine
10.1.10.2.1 DMA_NO_BUF
The DMA M2M Buffer FSM resets to the DMA_NO_BUF state. This state reflects that no
buffer descriptor has as yet been programmed in the DMA controller.
The DMA M2M Buffer FSM exits this state when one of the BCRx (x = 0 or 1) registers is
programmed. If BCR0 is written to, then the FSM moves to the DMA_BUF_ON state and
buffer0 becomes the active buffer available for a transfer. If BCR1 is written to then the FSM
moves to the DMA_BUF_ON state and buffer1 becomes the active buffer available for a
transfer.
10.1.10.2.2 DMA_BUF_ON
The DMA Buffer FSM enters the DMA_BUF_ON state from the DMA_NO_BUF state when
one of the BCRx registers is written to.
The DMA Buffer FSM enters the DMA_BUF_ON state from the DMA_BUF_NEXT state when
the transfer from the active buffer has ended. This end-of-buffer can be due to the BCRx
register value reaching zero, or receipt of a DEOT input from the external device (when in
external DMA transfer mode and DEOT is configured as an input signal to the DMA).
Data transfers to or from memory or external bus can occur in the DMA_BUF_ON state.
When the DMA Buffer FSM transitions from DMA_BUF_NEXT to DMA_BUF_ON state, the
NFB (Next Frame Buffer) interrupt is generated. This signals to software that rollover is
occurring to the other buffer and also that one of the BCRx registers is now free for update
DMA_NO_BUF
DMA_BUF_ON DMA_BUF_NEXT
BCRx_WRITE (x = 0 or 1)
Buffer End
BCRx_WRITE(x = 1 or 0)
Buffer End