Cirrus Logic EP93xx - Manual (Page 480)

12-2 DS785UM1
Copyright 2007 Cirrus Logic
Static Memory Controller
EP93xx User’s Guide
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The SMC has five main functions:
1. Memory bank selecting
2. Access timing
3. Wait State generation
4. Byte lane write enabling
5. External bus interfacing
12.2 Static Memory Controller Operation
The SMC provides access to static memory devices that are attached to the external bus.
The SMC can work with a wide variety of external device types, including SRAM, ROM, NOR
FLASH, and peripherals that respond to SRAM-type signaling.
Six chip-select output signals, CSn7, CSn6, CSn3, CSn2, CSn1, and CSn0 can be used to
access six different memory spaces. However, only one of the six memory banks can be
accessed at a given time. The SMC has six independent control registers that configure the
six respective chip-select signals. Each control register,
"SMCBCR[7:0]" specifies the timing
characteristics that are needed to access the memory device(s) in its respective memory
space.
As shown in Figure 12-1 and Figure 12-3 , the SMC captures read data on the HCLK edge
that occurs just prior to the HCLK edge that de-asserts the chip-select output signal on the
CSnX pin. The output signal on the CSnX pin and the address outputs on the AD[x] pins are
de-asserted on the next HCLK edge.
The SMC can insert wait cycles into its access timing. Wait cycles can be specified by:
• A programmable value, N, where N has the range 1<N<32. When N is used, the SMC
holds its bus state for N HCLK cycles. The value for N must be written to the WST2
and/or WST1 fields of the
"SMCBCR[7:0]" register(s).
• An asserted wait input signal on the WAITn pin. As shown in Figure 12-3 and Figure 12-
4 , the WAITn pin can be asserted as needed by an external device to extend access
time. When WAITn is asserted, the SMC holds its bus state until WAITn is sampled as
being de-asserted. For internal synchronization to occur,
WAITn must remain asserted
for a minimum of two HCLK cycles.
• When both N and WAITn are used, the SMC holds its bus state for N HCLK cycles or
until WAITn is sampled as being de-asserted, whichever occurs last.