Cirrus Logic EP93xx - Manual (Page 538)

14-16 DS785UM1
Copyright 2007 Cirrus Logic
UART1 With HDLC and Modem Control Signals
EP93xx User’s Guide
1
4
1
4
14
14.5.2 Bus Bandwidth Requirements
There are two basic ways of moving data to and from the UART FIFOs:
• Direct DMA interface - This permits byte-wide access to the UART without using the
APB. The DMA block will pack or unpack individual bytes so that it reads or writes full
32-bit words rather than individual bytes.
• Accessing the UART via the APB - This requires APB/AHB bus bandwidth. Then, both a
read and write are required for each 8-bit data byte.
Bandwidth requirements also depend on the selected baud rate, character size, parity
selection, number of stop bits, and spacing between characters (if receiving).
For example, assume transmission protocols of 115,200 baud, 8-bit characters, even parity,
one stop bit, no space between characters. There are 11 bits per character, so
115,200 / 11 = 10,473 characters per second. If both transmitting and receiving, 20,945
characters per second pass through the UART. Accessing the UART through the DMA
interface requires one access per 32-bits, implying only 20,945 / 4 = 5,236 AHB accesses per
second. Accessing the UART through the APB requires two accesses per byte, implying
20,945 APB bus accesses.
As another example, assume 230,400 baud (the maximum with a UARTCLK equal to
7.3728 Mhz), 5-bit characters, no parity, one stop bit, and no space between characters.
There are 7 bits per character, so 230,400 / 7 = 32,914 characters per second. Simultaneous
transmitting and receiving implies 65,829 characters per second. Using the DMA interface
would result in 16,457 AHB accesses per second, while using the APB to access the UART
leads to 65,829 bus accesses per second.