Cirrus Logic EP93xx - Manual (Page 650)

20-2 DS785UM1
Copyright 2007 Cirrus Logic
Real Time Clock With Software Trim
EP93xx User’s Guide
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20.1.1.1 Software Compensation
The 1 Hz clock is generated by running a programmable counter clocked by the 32.768 KHZ
crystal oscillator reference. If the crystal reference and oscillator were perfect, a counter that
counted 32768 clocks would provide a 1 Hz reference. However, the counter pre-load value
is programmable to allow inaccuracies in the crystal and oscillator circuit. Simply allowing a
different counter pre-load value only gives an accuracy of:
(½LSB / 32768 bits) x (3600 sec. / 1 hr) x (24hrs/day) x (30 days/month)
~= +/- 40 sec. per month
To further increase the accuracy, a fractional compensation is needed. This compensation
mechanism provides a much better nominal RTC accuracy. The 1 Hz clock feeding the RTC
is obtained by dividing the output of the 32.768 KHZ oscillator by an integer value. However,
factors such as inaccuracy of the crystal, varying capacitance of the board traces, leads, and
connections, etc., will cause the reference frequency to be inaccurate. This is corrected in
software by adjusting the 1 Hz clock period through an integer compensation (by adjusting
the counter preload) and with a fractional compensation (via deleting clocks at a fixed
interval). By measuring the frequency of the reference crystal, and setting the RTCSWComp
register value, the clock can be adjusted to a nominal accuracy of better than +/- 5 seconds
per month.
20.1.1.2 Oscillator Frequency Calibration
Manufacturing can use a high precision frequency counter to measure the RTC 32.768 kHz
reference clock via the EGPIO[1] pin when the RSTCR.RonG bit is set. This mode isolates
the measurement of the oscillator circuit during manufacturing test to avoid disturbing the
crystal reference frequency through added probe capacitance, etc. The compensation is
accomplished by dividing the output of the oscillator by a integer value (with a pre-loadable
counter) and then doing a fractional adjustment by periodically deleting clocks to the counter.
20.1.1.3 RTCSWComp Value Determination
After the true frequency of the oscillator is known, it is separated into integer and fractional
portions. The integer portion of the frequency (less one) is set as the counter pre-load value.
When the counter reaches zero, a carry pulse is generated and the counter is pre-loaded
again. The carry pulse is used as the RTC 1 Hz signal reference.
The fractional part of the adjustment is done by deleting clocks from the clock stream feeding
the integer counter. The period interval between deleting clocks is 32 seconds. The number
of clocks deleted is set by RTCSWComp.DEL[4:0].