Cirrus Logic EP93xx - Manual (Page 324)

9-22 DS785UM1
Copyright 2007 Cirrus Logic
1/10/100 Mbps Ethernet LAN Controller
EP93xx User’s Guide
9
9
9
Refer to the circled numbers in Figure 9-9 . The detailed receive flow is:
1. Driver initializes some number of receive descriptors.
2. Driver writes RXDEnq register with the additional number of receive descriptors.
3. On-chip Descriptor Processor fetches descriptors into internal FIFO decrements
RXDEnq appropriately.
4. The address of the next receive data buffer is loaded into the Receive Buffer Current
Address.
5. A frame is received from the LAN medium.
6. The MAC Engine passes the frame data to the Receive Data FIFO.
7. The Receive Descriptor Processor stores the frame data into system memory.
Note: Steps 5, 6, and 7 can overlap.
8. End of frame status is written to the Receive Status Queue the RXStsEnq value reduced
by one.
9. Driver interrupted if interrupt conditions met.
10.Received frame passed to the protocol stack.
11.Driver clears the Receive Frame Processed bit in Status Queue.
12.Driver writes number of entries processed in the status queue, freeing them for future
use by the MAC.
13.After the driver gets the used receive buffers back from the stack, the driver may repeat
step 2.
Note: Steps 1, 11, and 13 are transparent to the MAC. Steps 2 through 10 and 12 directly involve
the MAC.
9.2.3.3 Receive Errors
Receive error conditions are broken into two categories: hard errors and soft errors. A hard
error is generally considered a reliability problem. This includes AHB bus access problems. A
soft error indicates that the frame was not successfully received. The error may be expected
or rare. A soft error needs a graceful recovery by the host driver. Soft errors include: CRC
errors, receiver over-run, frames too long, or frames too short. Hard errors are parity errors
(when enabled), system errors, and master or target aborts, these errors will stop receive
DMA activity, and require host intervention for recovery. Recovery may be achieved by
performing a RxChRes (Bus Master Control) and reinitializing.