Cirrus Logic EP93xx - Manual (Page 76)

3-6 DS785UM1
Copyright 2007 Cirrus Logic
MaverickCrunch Co-Processor
EP93xx User’s Guide
3
3
3
72 bits wide. If the accumulator saturation mode is disabled (the default), the accumulator bit
fields are assigned as below for a 2’s complement integer.
If the saturation mode 1.63 is selected, the bit field assignments are:
If the saturation mode 1.31 is selected, the bit field assignments are:
If the saturation mode 2.62 is selected, the bit field assignments are:
3.1.6 Comparisons
The Crunch co-processor provides four compare operations:
• CFCMP32 - 32-bit integer
• CFCMP64 - 64-bit integer
• CFCMPS - single floating point
• CFCMPD - double floating point
The DSPSC register bit UINT affects the operation of integer comparisons. If clear, integers
are treated as signed values, and if set, they are treated as unsigned. DSPSC.UINT has no
effect on floating point comparisons.
All compare operations update both the FCC[1:0] bits in the DSPSC register and an ARM
register. Though any of the ARM general purpose registers r0 through r14 may be specified
as the destination, specifying r15 actually updates the CPSR flag bits NZCV. This permits the
Opcode
71 70 0
Sign Data
Opcode
71 64 63 62 0
Sign Extension Sign Data
Opcode
71 64 63 62 32 31 0
Sign Extension Sign Data Unused
Opcode
71 63 62 61 0
Sign Extension Sign Data