Cirrus Logic EP93xx - Manual (Page 131)

DS785UM1 5-5
Copyright 2007 Cirrus Logic
System Controller
EP93xx User’s Guide
5
5
5
Both PLLs are software programmable (each value is defined in “ClkSet1” on page 5-18 and
“ClkSet2” on page 5-20 registers, respectively). The frequency of output clock Fout is
determined by:
Here PLL1_X1FBD, PLL1_X2FBD, PLL1_X2IPD and PLL1_PS are the bit fields in the
"ClkSet1" register. The user must be aware of the requirements of PLL operation. They are:
• PLL1_X1 desired reference clock frequency range is > 11.058 MHz and < 200 MHz
• PLL1_X1 output frequency range is > 294 MHz and < 368 MHz
• PLL1_X2 desired reference clock frequency (after PLL1_X2IPD divider) is > 12.9 MHz
and < 200 MHz.
• PLL1_X2 output, BEFORE the PS divide, must be > 290 MHz and <= 528 MHz
The same conditions apply to PLL2 and the "ClkSet2" register.
5.1.5.2 Bus and Peripheral Clock Generation
Figure 5-2 illustrates the clock generation system.
Fout 14.7456MHz
PLL1_X1FBD 1 +
( )
PLL1_X2FBD 1 +
( ) ×
PLL1_X2IPD 1 +
( ) 2 PLL1_PS Ч
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