Uart3 with hdlc encoder, 1 introduction, 2 implementation details – Cirrus Logic EP93xx User Manual
Page 577: 1 uart3 package dependency, Chapter 16. uart3 with hdlc encoder -1, 1 introduction -1 16.2 implementation details -1, 1 uart3 package dependency -1, Table 16-1. uart3 pin functionality -1, Chapter 16, Uart3 with
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Copyright 2007 Cirrus Logic
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Chapter 16
16
UART3 With HDLC Encoder
16.1 Introduction
Note: This chapter applies only to the EP9307, EP9312, and EP9315 processors.
UART3 implements both a UART and an HDLC interface identical to that of UART1; it does
not implement the modem interface. An additional output signal, TENn, is provided to support
RS-485 operation by providing direction control of external data transceivers. The OUT1 and
OUT2 signals in the MCR register define the TENn operating mode. TENn can be configured
to assert whenever the UART transmit buffer has data to send, or to operate under software
control.
For additional details about UART1, refer to
,
16.2 Implementation Details
16.2.1 UART3 Package Dependency
UART3 uses package pins RXD2, TXD2 and EGPIO[3]. See
for details.
The use of EGPIO[3] is determined by several bits in Syscon register DeviceCfg. See
for details.
Table 16-1. UART3 Pin Functionality
PIN
Description
RXD2
UART2 input pin
TXD2
UART2 output pin
EGPIO[3]
HDLC clock or TENn