Cirrus Logic EP93xx - Manual (Page 37)

DS785UM1 1-9
Copyright 2007 Cirrus Logic
Introduction
EP93xx User’s Guide
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1.4.5 Integrated Ethernet MAC Reduces BOM Costs
The EP93xx processors integrate a 1/10/100 Mbps Ethernet Media Access Controller (MAC).
With a simple connection to MII-based external PHYs (such as the Cirrus Logic CS8952 PHY
Transceiver), an EP93xx processor-based system has easy, high-performance, cost-effective
Internet capability.
1.4.6 8x8 Keypad Interface Reduces BOM Costs
The EP9307, 9312, and 9315 processors include a matrix keypad controller that scans an
8x8 array of 64 normally open, single pole switches. Any one or two keys depressed will be
de-bounced and decoded. An interrupt is generated whenever a stable set of depressed keys
is detected. If the keypad is not utilized, the 16 column/row pins may be used as general-
purpose I/Os.
1.4.7 Multiple Booting Mechanisms Increase Flexibility
The EP93xx processors include a 16 KByte Boot ROM to set up standard configurations. The
Boot ROM controls booting from either FLASH memory, the SPI serial interface, or a UART.
This boot flexibility makes it easy to design user-controlled, field-upgradable systems. See
Chapter 4 on page 4-1 , for additional details. The EP93xx processors can also boot directly
from CSn0, bypassing the Boot ROM.
1.4.8 Abundant General Purpose I/Os Build Flexible Systems
The EP93xx processors include both enhanced and standard general-purpose I/O pins
(GPIOs). The enhanced GPIOs may individually be configured as inputs, outputs, or
interrupt-enabled inputs. Nineteen enhanced GPIOs are in EP9301 and 9302 processors, 18
are in the EP9307 processor, and 16 are in EP9312 processor, and 24 are in the EP9315
processor.
The standard GPIOs may individually be used as inputs, outputs, or (in some cases) open-
drain pins. The standard GPIOs are multiplexed with peripheral function pins, so the number
available depends on the utilization of peripherals. Eighteen standard GPIOs are in EP9301
and 9302 processors, 30 are in the EP9307 processor, 31 are in the EP9312 and EP9315
processors.
Together, the enhanced and standard GPIOs facilitate easy system design with external
peripherals not integrated on the EP93xx processors.
1.4.9 General-Purpose Memory Interface (SDRAM, SRAM, ROM, FLASH)
The EP93xx processors feature a unified memory address model in which all memory
devices are accessed over a common address/data bus. In the EP9301 and 9302
processors, the common address/data bus is 16-bits wide, the Static Memory Controller
(SMC) supports 8-bit and 16-bit devices and the SDRAM, SyncROM, and SyncFLASH
synchronous memory controller supports 16-bit devices. In the EP9307, EP9312, and
EP9315 processors, the common address/data bus is programmable to either 16-bits or 32-