3 ide dma programming considerations, 3 ide dma programming considerations -8 – Cirrus Logic EP93xx User Manual
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DS785UM1
Copyright 2007 Cirrus Logic
IDE Interface
EP93xx User’s Guide
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Note: This is the number of wait states required by the IDE Controller to deassert the DMA
Controller request line after each word transfer is complete.
27.2.7.3 IDE DMA Programming Considerations
This is a general guideline for programming the DMA controller to properly interact with the
IDE controller without receiving malformed data. All cases assume the DMA controller is
capable of burst read or burst write operations. Non-ideal DMA controllers may be able to
avoid wait-states due to less than optimal bus utilization.
27.2.7.3.1 General Note
Please verify that the DMA controller will ignore DMA requests if it's transfer counter register
has gone to zero. If this is not the case, the DMA controller must be configured to time out
based on the wait-state table in
. Quad-word bursts are not
allowed.
27.2.7.3.2 Multi-word DMA
Follow the wait-state number listed in the wait-state table in
. Quad-
word bursts are not allowed.
Table 27-3. Wait State Value for the DMA M2M Register Control.PWSC
Wait States:
Multi-Word DMA Request
Ultra DMA Request
Read 0
1
Write 3
2
Table 27-4. HCLK Cycles to De-assert DMA Request
Operation
HCLK Cycle
Event
Multi-word DMA Write to IDE Controller:
0
AHB write command
1
DMAide deasserts
Multi-word DMA Read from IDE Controller:
0
AHB read command
1
AHB read data, DMAide deasserts
Ultra DMA Write to IDE Controller:
0
AHB write command
1
Data stored in IDE register
2
Data stored in FIFO, FIFO status updates
3
DMAide deasserts
Ultra DMA Read from IDE Controller:
0
AHB read command
1
AHB read data, word counter updates
2
DMAide deasserts