Cirrus Logic EP93xx - Manual (Page 339)

DS785UM1 9-37
Copyright 2007 Cirrus Logic
1/10/100 Mbps Ethernet LAN Controller
EP93xx User’s Guide
9
9
9
9.2.4 Interrupts
9.2.4.1 Interrupt Processing
Interrupts can be associated with on chip status or with off-chip status. (Off-chip status is
status that has been transferred to either the transmit or receive status queue.) The status for
any outstanding interrupt event is available via two different register addresses: IntStsP
(Interrupt Status Preserve) and IntStsC (Interrupt Status Clear).
Reading the IntStsP register has no effect on the bits set in the register. They may be
explicitly cleared by writing a “1” back to any of the bit positions. This allows the Host to
process interrupt events across multiple routines, only clearing the bits for which it has
processed the corresponding events.
The IntStsC register will clear the status for all outstanding events when it is read. This
provides a quick mechanism for the Host to accept all the outstanding events in one read and
not incur the additional IO cycles required in specifically clearing the events.
9.2.5 Initialization
The following is the suggested hardware initialization sequence for a driver:
1. Determine what PHYs are available (poll PHYs via the management interface via
MICmd, MIIData, and MIISts registers.
2. Enable auto negotiation to determine the mode of operation 10/100 Mbit, FDX/HDX.
This may be needed to determine the amount of buffering to use.
3. Set RXDQBAdd and RXDCurAdd to point to the start of the receive descriptor queue
4. Set RXDQBLen to the length of the receive descriptor queue.
5. Set RXStsQBAdd and RXStsQCurAdd to point at the start of the receive status queue.
6. Set RXStsQBLen to the length of the status queue.
7. Set BMCtl.RxEn which clears the RXDEnq/RXStsEnq registers and initializes internal
pointers to the queues. No bus master activity is triggered by the enable, because the
enqueue registers are zero.
8. Set TXDQBAdd and TXDQCurAdd to point to the start of the transmit descriptor queue.
9. Set TXDQBLen to the length of the transmit descriptor queue.
10.Set TXStsQBAdd and TXStsQCurAdd to point to the start of the transmit status queue.
11.Set TXStsQBLen to the length of the status queue.
12.Set BMCtl.TxEn which clears the TXDEnq and initializes internal pointers to the
queues. No bus master activity is triggered by the enable because the enqueue register
is zero.
13.Set required interrupt mask and global interrupt mask (IntEn, GlIntMsk).