Cirrus Logic EP93xx - Manual (Page 561)

DS785UM1 15-3
Copyright 2007 Cirrus Logic
UART2
EP93xx User’s Guide
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A start bit is detected when the decoder input is LOW.
Regardless of being in normal or low-power mode, a start bit is deemed valid if the decoder is
still LOW, one period of IrLPBaud16 after the LOW was first detected. This allows a normal-
mode UART to receive data from a low-power mode UART, which may transmit pulses as
small as 1.41
μ
sec.
15.2.2 IrDA SIR Operation
The IrDA SIR Encoder/decoder provides functionality which converts between an
asynchronous UART data stream and half-duplex serial SIR interface. No analog processing
is performed on-chip. The role of the SIR encoder/decoder is only to provide a digital
encoded output and decoded input to the UART. There are two modes of operation:
• In normal IrDA mode, a zero logic level is transmitted as high pulse of 3/16
th
duration of
the selected baud rate bit period on the nSIROUT signal, while logic one levels are
transmitted as a static LOW signal. These levels control the driver of an infrared
transmitter, sending a pulse of light for each zero. On the reception side, the incoming
light pulses energize the photo transistor base of the receiver, pulling its output LOW.
This then drives the SIRIN signal LOW.
• In low-power IrDA mode, the width of the transmitted infrared pulse is set to 3 times the
period of the internally generated IrLPBaud16 signal (1.63 ns assuming a nominal
1.8432MHz frequency) by changing the appropriate bit in UARTCR.
In both normal and low-power IrDA modes, during transmission, the UART data bit is used as
the base for encoding, while during reception the decoded bits are transferred to the UART
receive logic.
The IrDA SIR physical layer specifies a half duplex communication link with a minimum 10ms
delay between transmission and reception. This delay must be generated by software since it
is not supported by the UART. The delay is required since the Infrared receiver electronics
may become biased or even saturated from the optical power coupled from the adjacent
transmitter LED. This delay is known as latency or receiver setup time. Shorter delays may
be able to be used when the link first starts up.
The IrLPBaud16 signal is generated by dividing down the UARTCLK signal according to the
low-power divisor value written to UARTILPR.
The low-power divisor value is calculated as:
Low-power divisor = (FUARTCLK / FirLPBaud16) -1
where FirLPBaud16 is nominally 1.8432 MHz.
The divisor must be chosen so that 1.42 MHz < IrLPBaud16 < 2.12 MHz.