6 hash filter, 6 hash filter -9, Figure 9-6. crc logic -9 – Cirrus Logic EP93xx User Manual

Page 311

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DS785UM1

9-9

Copyright 2007 Cirrus Logic

1/10/100 Mbps Ethernet LAN Controller

EP93xx User’s Guide

9

9

9

9.1.4.6 Hash Filter

The 64 bit Logical Address Filter provides DA filtering hashed by the CRC logic. The Logical
Address Filter is sometimes referred to as the multicast address filter.

Referring to

Figure 9-6

, notice that the CRC computation starts at the first bit of the frame,

which is also the first bit of the DA. (Recall that a “frame” is a “packet” without the preamble.)

The CRC Logic can be viewed as a 32 bit shift register with specific Exclusive-OR feedback
taps. After the entire DA has been shifted into the CRC Logic, the signal HashLat latches the
6 most significant bits of the CRC Logic (x

26

through x

31

) into the 6-bit hash register (HR). The

contents of HR are passed through the 6-bit to 64-bit Decoder. Only one of the 64 Decoder
outputs is asserted at a time. That asserted output is compared with a corresponding bit in
the Logical Address Filter. The filter output, Hashed, is used to determine if the received DA
passed the hash filter. When set, the Hashed event bit shows that the received DA passed
the hash filter. When clear, Hashed shows the failure of the DA to pass the hash filter.

Figure 9-6. CRC Logic

Whenever the hashed filter is passed on good frames, the output of the HR is presented on
the Hash Table Index (RStatQ). A received good frame is determined to be one without CRC
error and which is the correct length (64 < length < 1518).

If RXCtl.MA is set, then any received multicast frame passing the hash filter is accepted. A
multicast frame is one which has RXCtl.IA[0] = 1.

If RXCtl.IAHA[0] is set, then a frame with any individual address frame AND passing the hash
filter is accepted. An individual address frame is one which has RXCtl.IA[0] = 0. For a frame
to pass RXCtl.IAHA[0] it must have RXCtl.IA[0] = 0 and pass the hash.

CRC Logic (32 bit shift register with XOR taps)

Hash Register (HR)

6 bits

31

X

26

X

6 most significant
bits of the CRC

HashLat

Decoder

6 bit to 64 bit

64

Hash Table

64 bits

Hashed True = passed filter
Hashed False = failed filter

Hashed

The six HR output lines go to
the Hash Table Index

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