Cirrus Logic EP93xx - Manual (Page 529)

DS785UM1 14-7
Copyright 2007 Cirrus Logic
UART1 With HDLC and Modem Control Signals
EP93xx User’s Guide
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14
14.2.3 Interrupts
There are five interrupts generated by the UART. Four of these are individual maskable active
HIGH interrupts:
• UARTMSINTR
• UARTRXINTR
• UARTRTINTR
• UARTTXINTR
The interrupts are also output as a combined single interrupt UARTINTR.
Each of the four individual maskable interrupts is enabled or disabled by changing the mask
bits in UARTCR. Setting the appropriate mask bit HIGH enables the interrupt.
The transmit and receive dataflow interrupts UARTRXINTR and UARTTXINTR have been
separated from the status interrupts. This allows UARTRXINTR and UARTTXINTR to be
used in a DMA controller, so that data can be read or written in response to just the FIFO
trigger levels. The status of the individual interrupt sources can be read from UARTIIR.
14.2.3.1 UARTMSINTR
The modem status interrupt is asserted if any of the modem status lines (nUARTCTS,
nUARTDCD and nUARTDSR) change. It is cleared by writing to the UART1IntIDIntClr
register.
This interrupt is not independently connected to the system interrupt controller.
14.2.3.2 UARTRXINTR
The receive interrupt changes state when one of the following events occurs:
If the FIFOs are enabled and the receive FIFO is half or more full (it contains eight or more
words), then the receive interrupt is asserted HIGH. The receive interrupt is cleared by
reading data from the receive FIFO until it becomes less than half full.
If the FIFOs are disabled (have a depth of one location) and data is received thereby filling
the location, the receive interrupt is asserted HIGH. The receive interrupt is cleared by
performing a single read of the receive FIFO.
This interrupt is connected to the system interrupt controller.
14.2.3.3 UARTTXINTR
The transmit interrupt changes state when one of the following events occurs:
• If the FIFOs are enabled and the transmit FIFO is at least half empty (it has space for
eight or more words), then the transmit interrupt is asserted HIGH. It is cleared by filling
the transmit FIFO to more than half full.