2 8 bpp word layout, 3 16 bpp word layout – Cirrus Logic EP93xx User Manual
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Copyright 2007 Cirrus Logic
Graphics Accelerator
EP93xx User’s Guide
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8.5.2.2 8 BPP Word Layout
For a Block Copy where 4 pixels are transferred per scan line, let the starting SDRAM
address of the source image be 0x0000.
shows that Pixel 2 starts at bit 16, Pixel 3
starts at bit 24, etc. The start pixel, P2, is in the word at address 0x0000 and has a beginning
bit position of 16. This makes 16 = 0x10 the value that is used for the SPEL field in the
register.
Let the starting SDRAM address of the destination image be 0x0030.
shows that
Pixel 2 starts at bit 16, Pixel 3 starts at bit 34, etc. The start pixel, P2, is in the word at address
0x0030 and has a beginning bit position of 16. This makes 16 = 0x10 the value that is used
for the SPEL field in the
register.
The end pixel, P5, is in the word at address 0x0034 and has a beginning bit position of 8. This
makes 8 = 0x8 the value that is used for the EPEL field in the
register.
Note:The word count for this example would be: 2 - 1 = 1 words, since P5 ends in the 2nd word.
So, WIDTH = 0x1 would be written to the
register.
8.5.2.3 16 BPP WORD Layout
For a Block Copy where 8 pixels are transferred per scan line, let the starting SDRAM
address of the source image be 0x0000.
shows that Pixel 0 starts at bit 0, Pixel 1
starts at bit 16, etc. The start pixel, P0, is in the word at address 0x0000 and has a beginning
bit position of 0. This makes 0 = 0x0 the value that is used for the SPEL field in the
register.
Table 8-15. 8 BPP Memory Layout for Source Image
Address
31
24
23
16
15
8
7
0
0x0000
P3
P2
P1
P0
0x0004
P7
P6
P5
P4
Table 8-16. 8 BPP Memory Layout for Destination Image
Address
31
24
23
16
15
8
7
0
0x0030
P3
P2
P1
P0
0x0034
P7
P6
P5
P4
Table 8-17. 16 BPP Memory Layout for Source Image
Address
31
16
15
0
0x0000
P1
P0
0x0004
P3
P2
0x0008
P5
P4
0x000C
P7
P6