2 registers, 2 registers -9, Table 28-5. gpio register address map -9 – Cirrus Logic EP93xx User Manual

Page 799

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DS785UM1

28-9

Copyright 2007 Cirrus Logic

GPIO Interface

EP93xx User’s Guide

2

8

2

8

28

10. COL[7:0] are the Key Matrix column pins.

Note: The various functional modes described in

Table 28-4

are selected via bits set in the

DeviceCfg register in Syscon. See

Chapter 5

,

“DeviceCfg” on page 5-25

for additional

register information.

When the GPIO port signals are not explicitly mapped to a device pin, the inputs will continue
to monitor the pin while outputs are disconnected. For example, when the Key Matrix block
has control of the ROW pins, GPIO port C inputs still monitor the state of the ROW pins.

Another level of functional muxing is applied to several EGPIO pins. The Syscon DeviceCfg
register bits RonG, MonG, TonG, HC3EN, HC1EN, and map different functionality to the
EGPIO pins:

MonG maps RI (modem Ring Indicator) onto EGPIO[0].

RonG maps CLK32K, the 32 KHz clock monitor output for RTC calibration, onto

EGPIO[1].

TonG maps TENn, the RS485 transmit enable output, onto EGPIO[3].

Both HC3EN and HC1EN map the synchronous HDLC clock onto EGPIO[3].

Some GPIO signals are used as inputs by other functional blocks. EGPIO[2:1] are routed to
the DMA controller to allow for external DMA requests. IDE interface input signals DMARQ
and DASPn are EGPIO[2] and EGPIO[15], respectively.

28.2 Registers

Table 28-5. GPIO Register Address Map

Address

Read Location

Type

Write Location

Reset Value

0x8084_0000

PADR R/W

PADR

Note

1

0x8084_0004

PBDR R/W

PBDR

Note

1

0x8084_0008

PCDR R/W

PCDR

Note

1

0x8084_000C

PDDR R/W

PDDR

Note

1

0x8084_0010

PADDR R/W

PADDR

0x00

0x8084_0014

PBDDR R/W

PBDDR

0x00

0x8084_0018

PCDDR R/W

PCDDR

0x00

0x8084_001C

PDDDR R/W

PDDDR

0x00

0x8084_0020

PEDR R/W

PEDR

Note

2

0x8084_0024

PEDDR R/W

PEDDR

0x03

0x8084_0028

RSVD

-

RSVD

-

0x8084_002C

RSVD

-

RSVD

-

0x8084_0030

PFDR R/W

PFDR

Note

1

0x8084_0034

PFDDR R/W

PFDDR

0x00

0x8084_0038

PGDR R/W

PGDR

Note

1

0x8084_003C

PGDDR R/W

PGDDR

0x0C

0x8084_0040

PHDR R/W

PHDR

Note

1

0x8084_0044

PHDDR R/W

PHDDR

0x00

0x8084_0048 RSVD

-

RSVD

-

0x8084_004C

GPIOFIntType1 R/W

GPIOFIntType1

0x00

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