7 dma request latency, 1 dma request deassertion, 2 dma request latency overview – Cirrus Logic EP93xx User Manual
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Copyright 2007 Cirrus Logic
IDE Interface
EP93xx User’s Guide
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latching of the data. It is calculated that the cycle time of AHB clock has to be smaller than
(IDE cycle time)*2/3. For different UDMA speed modes, the minimum AHB clock speeds are
listed below. There is no special speed constraint imposed on the design for PIO and MDMA
modes.
27.2.7 DMA Request Latency
27.2.7.1 DMA Request Deassertion
Multi-word DMA Write to IDE Controller:
The DMAide signal deassertion is generated based on the AHB write logic. The act of writing
to the Multi-word DMA write-FIFO causes the deassertion to appear on the following bus
cycle.
Multi-word DMA Read from IDE Controller:
The DMAide signal deassertion is generated based on the AHB read logic. The act of
reading from the Multi-word DMA read-FIFO causes the deassertion to appear on the
following bus cycle.
Ultra DMA Write to IDE Controller:
The DMAide signal deassertion is generated based on the contents of the Ultra DMA write
FIFO. If the FIFO contains four or more elements, the DMAide signal deasserts.
Ultra DMA Read from IDE Controller:
The DMAide signal deassertion is generated based on an internal counter. The DMAide
signal will deassert if four DMA reads have occurred or if the FIFO is now empty (which only
occurs at the end of a non-quad word aligned read from the IDE device)
27.2.7.2 DMA Request Latency Overview
The IDE controller requires a certain number of cycles to deassert the DMA request line
DMAide after a DMA access for Multi-word DMA and Ultra DMA modes. The number of wait-
states required are listed below in addition to the pipeline breakdown of the signal
propagation. The assumption is that the deassertion should follow an AHB bus command
(read or write) in HCLK cycle 1.
Table 27-2. IDE Cycle Times and Data Transfer Rates
UDMA Speed Mode
Min. IDE Cycle Time
Max. AHB Cycle
Time
Min. AHB Clock
Frequency
0
112 ns
74.7 ns
13.4 MHz
1
73 ns
48.7 ns
20.5 MHz
2
54 ns
36.0 ns
27.8 MHz
3
39 ns
26.0 ns
38.5 MHz
4
25 ns
16.7 ns
59.8 MHz