Cirrus Logic EP93xx - Manual (Page 398)

10-4 DS785UM1
Copyright 2007 Cirrus Logic
DMA Controller
EP93xx User’s Guide
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The transaction is initiated by a SSP or IDE request.This request is masked after each
peripheral width transfer, in order to allow latency for the peripheral to deassert its
request line.The transfer terminates when the Byte Count Register equals zero.
• Memory and External Bus.
These can be memory- or FIFO-based and memory-mapped through the SMC.
Working with peripheral devices may optionally use the external signals DREQ, DACK
and DEOT/TC to control the data transfer using the following rules:
• The peripheral sets a request for data to be read-from/written-to by asserting DREQ.
• The peripheral transfers/samples the data when DACK is asserted.
• To terminate the current transfer, depending on the programmed direction of
DEOT/TC, the peripheral asserts DEOT coincident with DREQ or the DMA asserts
TC coincident with DACK.
These data transfer handshaking signals are optional: if the external device doesn’t use
them, then the transfer will operate like an internal peripheral transfer. To support an external
DMA peripheral, each request generates one peripheral-width DMA transfer. The M2M
Channel 0 is dedicated to servicing External device 0 and the M2M Channel 1 is dedicated to
servicing External device 1.
10.1.3.2 Memory-to-Peripheral Channels
The 5 M2P and 5 P2M channels support data transfers between Memory and Internal
Peripherals (which are byte-wide). Five dedicated channels are available to transfer data
between internal peripheral and memory (receive direction), and five channels are available
to transfer data between memory and peripheral (transmit direction). Transfers are controlled
using a REQ/ACK handshake protocol supported by each peripheral.
10.1.4 Internal M2P or P2M AHB Master Interface Functional Description
The AHB Master interface is used to transfer data between the system memory and the DMA
Controller internal M2P/P2M channels in both receive and transmit directions as follows:
• In the receive direction, data is transferred to system memory from a packer unit.
• In the transmit direction, data is transferred from the system memory into the unpacker
unit.
The AHB bus burst transfer size is a quad-word, that is, if the base memory address
programmed into the BASEx register is quad-word aligned then a quad-word transfer either
to memory from the 16-byte receive packer, or from memory to the 16-byte transmit packer is
carried out.
The internal M2P RxEnd signals are asserted by the peripheral to indicate the end of
received data or a receiver error. This causes the AHB master interface to write any valid
data in the receive packer to main memory. If RxEnd signals an error in receive data, and if
the ICE bit (Ignore Channel Error) is set, then the DMA continues transfers as normal. The
RxEnd is asserted by the peripheral coincident with the last good data before the overrun