1 introduction, 1 introduction -1, Chapter 7 – Cirrus Logic EP93xx User Manual
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Copyright 2007 Cirrus Logic
Raster Engine With Analog/LCD Integrated Timing and Interface
EP93xx User’s Guide
7
7
7
Chapter 7
7
Raster Engine With Analog/LCD Integrated
Timing and Interface
7.1 Introduction
Note: This chapter applies only to the EP9307, EP9312, and EP9315 processors. For additional
information regarding the use of t he EP93XX Raster Engine, see the application note,
AN269, “Using the EP93xx’s Raster Engine” at:
.
The Raster engine is capable of providing data and timing signals for a variety of displays.
The engine has fully programmable video interface timings for progressive, dual scan, and
interlaced displays. This programmable interface also allows the raster engine to generate a
First Line Marker on the VSYNC line required by many low cost passive LCD displays.
Separate DAC interface signals are provided to allow analog RGB signal generation for
analog LCD displays or CRTs. The circuitry is also designed to generate CCIR656 4:2:2
YCrCb digital video output signals for interfacing with an NTSC encoder.
The Raster engine has an 18-bit pixel output bus. The engine also includes support for an 8-
bit parallel display interface for attaching to low-end display modules with integrated
controller and frame buffer. All control register accesses are memory mapped as single word
values and cannot be accessed as 8-bit or 16-bit memory values.
The Raster engine also provides hardware accelerated cursor support. The cursor size is
programmable up to 64 pixels wide by 64 pixels in height, and it can be stored anywhere in
memory as a 2 bpp bitmap image. The Raster Cursor accesses system memory to fetch the
cursor image data that will be automatically blended with the video image.
The Raster Display AHB bus master can be attached directly to SDRAM Port 0 via a side-
band bus or to any SDRAM port connected to the system AHB. If the raster engine is
connected to the system AHB, the selection bits in the
register determine which
of the 4 SDRAM chip selects are used for display buffer access. The choice of which bus to
use should be based on video bandwidth requirements and should be selected before video
services are activated. For systems with low to moderate video bandwidth, the Raster
Display can be attached to SDRAM Port 0 via the side-band bus. This setup allows some
parallelism in bus traffic, but suffers from slow AHB access to external memory. If the video
bandwidth requirements are high, or there is an expectation of low competing traffic, then the
Raster Display should be attached to the AHB and the Arbiter priority should be set to give
the Raster Display highest priority. This attachment gets the best bandwidth available for the
display, but other system performance will suffer.