Cirrus Logic EP93xx - Manual (Page 662)

21-6 DS785UM1
Copyright 2007 Cirrus Logic
I 2 S Controller
EP93xx User’s Guide
2
1
2
1
21
• Programmable first data bit position. that is, I
2
S or non-I
2
S format.
• Programmable left or right data word justification.
• Programmable data shift direction, that is, MSB or LSB received first.
• Data overflow detection.
• Clock domain synchronization.
• DMA accesses.
The basic operation of the I
2
S receiver is that data is serially shifted in to form a pair of left /
right words. This pair of words is written to a FIFO, which the ARM will read.
21.3.1 Receiver FIFO’s
Each channel has a 16 deep by 32 bit wide FIFO where the ARM or DMA controller can read
up to 8 sets of left / right data pairs. In order to receive left and right stereo data into the FIFO
and read this data out from the FIFO, the following sequence of events must be performed by
the programmer:
1. Enable the I
2
S controller.
The I
2
S global control register bit, I2SGlCtrl[0], must be written to in order to turn on the
PCLK to the I
2
S controller. The I
2
S controller will not function correctly if this is not done.
2. Enable the receive channel.
The channel corresponding to the FIFO must be enabled in order for it to start sampling
the data line. After being enabled, the I
2
S controller will wait until the start of the next
incoming left stereo word as indicated by the audio word clock. When the start of the left
word occurs, the I
2
S controller will sample the data line and load each bit into a
dedicated left shift register. At the end of the left word and start of the right word as
indicated by the audio word clock, the contents of the left shift register are loaded into a
left data register. The I
2
S controller will continue to sample the data line loading each bit
into a dedicated right shift register. At the end of the right word and start of the next left
word, the contents of the right shift register are loaded into a right data register. One
complete left and right stereo sample has now been received.
At this point, the I
2
S controller signals to the FIFO that there is valid data ready to be
written to the FIFO. The I
2
S controller will then write this stereo sample to FIFO location
0, which consists of 2 x 32 bit registers (assuming that this is the first sample to be
received). The FIFO-empty bit in the I
2
S Global Control Status register (I2SGlSts) is
now de-asserted. As more stereo sample pairs are received, they will be written to
locations 1, 2, 3 and so on.
The programmer can determine from the Global Control Status register if the FIFO has
any valid left / right stereo samples. These samples are obtained from the FIFO via the
APB by reading from the I2SRX0Lft and I2SRX0Rt registers. (See “Register