Cirrus Logic EP93xx - Manual (Page 531)

DS785UM1 14-9
Copyright 2007 Cirrus Logic
UART1 With HDLC and Modem Control Signals
EP93xx User’s Guide
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14.4.1 Overview of HDLC Modes
HDLC may operate in one of two basic modes, synchronous or asynchronous. Most
configuration options affect both modes identically. Setting the UART1HDLCCtrl.SYNC bit
selects synchronous mode and clearing it selects asynchronous mode. In asynchronous
mode, each byte is transmitted using standard UART protocol framing (that is, start bit, data,
parity, stop bit(s)). In synchronous mode, UART framing is bypassed.
The synchronous HDLC bit stream may be either a NRZ or Manchester encoded. In NRZ
mode, both the transmitter and receiver may be synchronized to either an external or internal
clock running at one cycle per bit period. The transmitter and receiver may operate
independently in any of the four modes:
• Simple NRZ mode
• Manchester encoded
• NRZ mode with an internal clock
• NRZ mode with an external clock
In the first NRZ mode, the data stream does not contain an explicit or implicit clock, so
synchronization between an HDLC transmitter and receiver cannot be guaranteed. A data bit
value of “1” is encoded as a one in the bit stream, and a value of “0” as a zero.
The second mode, Manchester encoding, combines the HDLC data and clock into a single bit
stream. In Manchester encoding, a transition always occurs in the middle of a transmitted bit
and the value after this transition is the actual value of the bit. That is, a “0” bit is represented
by a transition from high to low, and a “1” bit by a transition from low to high. Because a
transition always occurs in the middle of a bit, the receiver can always extract the proper data
after a suitable period of synchronization, provided the signal quality is good.
The third and fourth modes utilize NRZ encoding of the data accompanied by a separate
clock signal. The period of the clock signal is one bit period. When using an internal clock, the
HDLC transmitter generates a clock such that the data is stable at the clock’s rising edge.
Hence, an external receiver may sample each data bit at the rising edge of the clock. The
internal receiver will also use the same clock to sample input data if programmed to do so.
The internal transmitter and/or receiver may also synchronize to an external, rather than
internal, clock. The internal receiver gets this clock along with the incoming HDLC data,
allowing it to always sample bits at the right time. In addition, the internal transmitter will
synchronize the data it transmits to this clock if programmed to do so. The transmitter will
insure that its data is valid before the rising edge of the clock, and the receiver expects the
same of the incoming bit stream.
14.4.2 Selecting HDLC Modes
By default, HDLC is NRZ-encoded. Set bit UART1HDLCCtrl.TXENC to force Manchester
encoding in the transmitter, and set bit UART1HDLCCtrl.RXENC to make the receiver expect
Manchester encoding.