4 gpiotxcomplete, 5 slot2int, 6 slot1txcomplete – Cirrus Logic EP93xx User Manual

Page 693: 7 slot2txcomplete, 3 system loopback testing, 4 registers, 3 system loopback testing -5 22.4 registers -5, Table 22-2. ac’97 register memory map -5

Advertising
background image

DS785UM1

22-5

Copyright 2007 Cirrus Logic

AC’97 Controller

EP93xx User’s Guide

2

2

2

2

22

22.2.2.4 GPIOTXCOMPLETE

The transmit GPIOTXCOMPLETE interrupt is asserted when all values written to the
AC97S12Data have been transmitted. It is cleared when any data is written to the
AC97S12Data.

22.2.2.5 SLOT2INT

The receive SLOT2INT interrupt is asserted when the AC97S2Data register has new data
that has not been read. By reading the data in the AC97S2Data register the SLOT2INT
interrupt is cleared.

22.2.2.6 SLOT1TXCOMPLETE

The transmit SLOT1TXCOMPLETE interrupt is asserted when all values written to the
AC97S1Data have been transmitted. It is cleared when any data is written to the
AC97S1Data.

22.2.2.7 SLOT2TXCOMPLETE

The transmit SLOT2TXCOMPLETE interrupt is asserted when all values written to the
AC97S2Data have been transmitted. It is cleared when any data is written to the
AC97S2Data.

22.3 System Loopback Testing

A loopback test mode is available for system testing so that data transmitted on SDATAOUT
can also be received on SDATAIN. Loopback mode is entered when a “1” is written to the
LOOP bit in AC97GCR register. For normal operation the LOOP bit must always be “0”,
which is also the default state at reset.

Note: For this test mode to work, an external bit clock will need to be supplied.

22.4 Registers

Table 22-2. AC’97 Register Memory Map

Address

Type

Name

Description

0x8088_0000

Read/Write

AC97DR1

Data read or written from/to FIFO1

0x8088_0004

Read/Write

AC97RXCR1

Control register for receive

0x8088_0008

Read/Write

AC97TXCR1

Control register for transmit

0x8088_000C

Read

AC97SR1

Status register

0x8088_0010

Read

AC97RISR1

Raw interrupt status register

0x8088_0014

Read

AC97ISR1 Interrupt

Status

0x8088_0018

Read/Write

AC97IE1 Interrupt

Enable

0x8088_001C

- -

Reserved

0x8088_0020

Read/Write

AC97DR2

Data read or written from/to FIFO2

0x8088_0024

Read/Write

AC97RXCR2

Control register for receive

0x8088_0028

Read/Write

AC97TXCR2

Control register for transmit

0x8088_002C

Read

AC97SR2 Status

register

Advertising