Cirrus Logic EP93xx - Manual (Page 396)

10-2 DS785UM1
Copyright 2007 Cirrus Logic
DMA Controller
EP93xx User’s Guide
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• Five hardware requests for M2M transfers; 2 for external peripherals that follow the
handshake protocol, and 3 simple requests from IDE, SSPRx and SSPTx.
• Independent source and destination address registers. Source and destination can be
programmed to auto-increment or not for Memory-to-Memory channels.
• Two buffer descriptors per M2P/P2M and M2M channel to avoid potential data
underflow/overflow due to software introduced latency.
• For the internal M2P/P2M channels, buffer size is independent of the peripheral’s packet
size. Transfers can automatically switch between buffers.
• Per channel maskable interrupt generation.
• For DMA Data transfer sizes, byte, word and quad-word data transfers are supported
using a 16-byte data bay. Programmable max data transfer size per M2M channel.
• Per-channel clock gating reduces power in channels which have not been enabled by
software.
10.1.2 Managing Data Transfers Using a DMA Channel
A set of control and status registers are available to the system processor for setting up DMA
operations and monitoring their status, and monitoring system interrupts generated when any
of the DMA channels wish to inform the processor to update the buffer descriptor. The DMA
controller can service 10 out of 20 possible peripherals using the 10 internal M2P/P2M DMA
channels, each with its own peripheral DMA bus capable of transferring data in both
directions simultaneously.
The UART1/2/3 and IrDA can each use two DMA channels, one for transmit and one for
receive. The AC’97 interface can use six DMA channels (three transmit and three receive) to
allow different sample frequency data queues to be handled with low software overhead. The
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S interface can also use up to six DMA channels (three transmit and three receive) to allow
up to six channels of audio out and six channels of audio in.
To perform block moves of data from one memory address space to another with minimum of
program effort and time the DMA controller includes a memory-to-memory transfer feature.
An M2M software trigger capability is provided. It can also fill a block of memory with data
from a single location.
A hardware trigger is also provided for internal peripherals (IDE or SSP) or for external
peripherals which don’t use a handshaking protocol, to allow data streams between their
internal memory location (or the SMC) and the system memory.
For byte or word wide peripherals, the DMA can be programmed to request byte- or word-
wide AHB transfers respectively.
The transfer is completed when the Byte Count Register of the active buffer descriptor
reaches zero. Status bits will indicate if the actual byte count is equal to the programmed limit.
Completion of transfer will cause a DMA interrupt on that channel and rollover to the “other”
buffer descriptor, if configured.