Table 12-6, Table 12-7, N in – Cirrus Logic EP93xx User Manual
Page 487
DS785UM1
12-9
Copyright 2007 Cirrus Logic
Static Memory Controller
EP93xx User’s Guide
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2
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12
Table 12-6. Accesses to 8-Bit Attribute / Common / IO Memory
Common / IO
Memory Access
Attribute
Memory Access
Access
Byte #
In Word
PC_A[25:0]
nPC_CE2
nPC_CE1
D15-D8
D7-D0
D15-D8
D7-D0
Word
(4 transfers
required)
0
[25:2],x,0
0
0
-
[7:0]
-
[7:0]
1
[25:2],x,1
1
0
-
[15:8]
-
Invalid
2
[25:2],x,0
0
0
-
[23:16]
-
[23:16]
3
[25:2],x,1
1
0
-
[31:24]
-
Invalid
Lower
Half-Word
(2 transfers
required)
0
[25:2],x,0
0
0
-
[7:0]
-
[7:0]
1
[25:2],x,1
1
0
-
[15:8]
-
Invalid
Upper
Half-Word
(2 transfers
required)
2
[25:2],x,0
0
0
-
[23:16]
-
[23:16]
3
[25:2],1,1
1
0
-
[31:24]
-
Invalid
Byte
0
[25:2],x,0
0
0
-
[7:0]
-
[7:0]
Byte
1
[25:2],x,1
1
0
-
[15:8]
-
Invalid
Byte
2
[25:2],x,0
0
0
-
[23:16]
-
[23:16]
Byte
3
[25:2],x,1
1
0
-
[31:24]
-
Invalid
Table 12-7. Accesses to 16-Bit Attribute / Common / IO Memory
Common / IO
Memory Access
Attribute
Memory Access
Access
Half-Word
# IN Word
Processor
Address Bus
AD[25:0]
nPC_CE
2
nPC_CE
1
D15-D8
D7-D0
D15-D8
D7-D0
Word
(2
transfers
required)
0
AD[25:2],x,x
0
0
[15:8]
[7:0]
Invalid
[7:0]
1
AD[25:2],x,x
0
0
[31:24]
[23:16]
Invalid
[23:16]
Lower
Half-Word
0
AD[25:2],x,x
0
0
[15:8]
[7:0]
Invalid
[7:0]
Upper
Half-Word
1
AD[25:2],x,x
0
0
[31:24]
[23:16]
Invalid
[23:16]
Byte 0
0
AD[25:2],x,0
1
0
-
[7:0]
-
[7:0]
Byte 1
0
AD[25:2],0,1
1
0
[15:8]
-
Invalid
-
Byte 2
1
AD[25:2],x,0
1
0
-
[23:16]
-
[23:16]
Byte 3
1
AD[25:2],x,1
1
0
[31:24]
-
Invalid
-