1 free running mode, 2 pre-load mode, 3 40-bit timer operation – Cirrus Logic EP93xx User Manual

Page 636: 2 registers, 1 free running mode -2 18.1.2.2 pre-load mode -2, 3 40-bit timer operation -2, 2 registers -2, Table 18-1. timers register map -2

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18-2

DS785UM1

Timers
EP93xx User’s Guide

18.1.2.1 Free Running Mode

In free running mode, counters TC1 and TC2 will wrap to 0xFFFF when they reach zero
(underflow), and continue counting down. Counter TC3 will wrap to 0xFFFFFFFF when it
underflows, and continues counting down.

18.1.2.2 Pre-load Mode

In pre-load (periodic) mode, the value written to the TC1, TC2 or TC3 Load registers is
automatically re-loaded when the counter underflows. This mode can be used to generate a
programmable periodic interrupt.

18.1.3 40-bit Timer Operation

The time stamp debug timer is a 40-bit up-counter used only for long term debugging (TC4).
Its clock source is the 14.7456 MHz clock, divided by 15 to give a 983.04 kHz reference. The
timer value may be read at any time by reading the lower 32-bit word first and then the high
byte. Dividing the result by 983 yields a timestamp in milliseconds. The debug timer does not
cause an interrupt. The timer is controlled by a single enable bit. When the timer is enabled, it
begins counting from zero and when it is disabled, it is cleared back to zero. When it reaches
its maximum value (0xFF_FFFF_FFFF) it wraps around to zero and continues counting
upwards.

18.2 Registers

Table 18-1. Timers Register Map

Address

Read Location

Write Location

Size

Reset Value

0x8081_0000

"Timer1Load,"

16 bits

0x8081_0004

"Timer1Value,"