Cirrus Logic EP93xx - Manual (Page 337)

DS785UM1 9-35
Copyright 2007 Cirrus Logic
1/10/100 Mbps Ethernet LAN Controller
EP93xx User’s Guide
9
9
9
Refer to Figure 9-16 . The detailed transmit flow is:
1. Protocol stack initiates a transmit frame.
2. Driver parses protocol stack buffer into Transmit Descriptor Queue.
3. Driver writes number of additional entries to the Transmit Enqueue register.
4. On-chip Descriptor Processor fetches descriptor information.
5. On-chip Descriptor Processor initiates data move.
6. Frame data fetched from system memory into the transmit FIFO.
7. Frame transmitted onto LAN medium. Steps 6 and 7 can overlap.
8. End of frame status written to status queue
9. Driver interrupted if interrupt conditions met.
10.Driver processes the transmit status
11.Driver informs the protocol stack that transmit is complete.
Note: Steps 1, 2, 10, and 11 are transparent to the MAC block. Steps 3 through 9, inclusive,
directly involve the MAC.
9.2.3.13 Transmit Errors
Transmit error conditions are broken into two categories: hard errors and soft errors. A hard
error is generally considered a reliability problem. This includes AHB bus access problems. A
soft error indicates that the frame was not successfully transmitted. The error may be
expected or rare. A soft error needs a graceful recovery by the host driver. Soft errors include:
excessive collisions, SQE error (if connected to a MAU). Hard errors are parity errors (if
enabled), system errors, master and target aborts. These will stop further transmit DMA
activity and require host intervention for recovery.
Hard errors cause the Descriptor Processor to halt operation. This allows the Host to
determine the cause of error and reinitialize and restart the bus master operations.
Most soft errors do not cause the frame processing operations to halt. The Descriptor
Processor simply flags the error and continues on to the next frame. The exception is on a
transmit underrun. By halting the transmit frame processing, the Host has the ability to re-
initialize the transmit Descriptor Processor registers to point to the start of the failed frame
and re-initialize. This will cause the MAC to reattempt the failed frame and allows the order of
frame transmission to be maintained.